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參數(shù)資料
| 型號(hào)： | CY2212 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大?。?/td> | 124K |
| 代理商： | CY2212 |
CY2212
Document #: 38-07466 Rev. **
Page 4 of 10
Functional Specifications
This section gives the detailed functional specifications of the
device physical layer. These specifications refer to the logical
and physical interfaces.
Crystal Input
The CY2212 receives its reference from an external crystal.
Pin XIN is the reference crystal input, and pin XOUT is the
reference crystal feedback. The parameters for the crystal are
given on page 3 of this data sheet.
Select Input
There is only one select input, pin S. This pin selects the
frequency multiplier in the PLL, and is a standard LVCMOS
input. The S pin has an internal pull-up resistor. The multiplier
selection is given on page 1 of this data sheet.
LCLK Output Driver
In addition to the Rambus clock driver outputs, there is another
clock output driver. The LCLK driver is a standard LVCMOS
output driver.
Figure 1
below shows the LCLK output driver
load circuit.
RSL Clock Output Driver
Figure 2
shows the clock driver equivalent circuit.
The differential driver has a low output impedance in the range
of about 20 ohms. The driver also produces a specified voltage
swing on the channel. The nominal value of the channel
impedance, Z
CH
, is 28 ohms. Series resistor RS and parallel
resistor RP are used to set the voltage swing on the channel.
The driver output characteristics are defined together with the
external components, and the output clock is specified at the
measurement point indicated in
Figure 2
. The complete set of
external components for the output driver, including edge-rate
filter capacitors required for system operation, are shown in
Figure 3
. The values for the external components are given in
Table 1
.
Notes:
10. LCLK cycle jitter and 10-cycle jitter are defined as the difference between the measured period and the nominal period as defined on page 8.
11.
LCLK 10-cycle jitter specification is based on the measured value of LCLK cycle jitter as defined on page 8.
The output clocks drive transmission lines, potentially long
lines. Since circuit board traces will act as lossy, imperfectly
terminated transmission lines with some discontinuities, there
will be reflections generated which will travel back to the
DRCG-Lite output driver. If the output impedance does not
match ZCH, secondary reflections will be generated that will
add to position-dependent timing uncertainty. Therefore, the
CY2212 not only provides proper output voltage swings, but
also provides a well-matched output impedance. The driver
impedance, R
OUT
, is in series with R
S
, and the combination is
in parallel with R
P
.
t
CR
, t
CF
t
CR, CF
Output rise and fall times (measured at 20%
–
80% of output voltage)
Difference between output rise and fall times on the same pin of a single
device (20%
–
80%)
PLL loop bandwidth
250
500
100
ps
ps
BW
LOOP
50 kHz
(
–
3 dB)
106.6
8 MHz
(
–
20 dB)
142.2
1
0.8
t
CYCLE,L
t
LR
, t
LF
t
JC,L
t
J10,L
DC
L
LCLK clock cycle time
LCLK output rise and fall time
LCLK cycle jitter
[10]
LCLK 10-cycle jitter
[10,11]
LCLK output duty cycle
ns
ns
ns
ns
–
0.8
–
1.1 * t
JC,L
1.1 * t
JC,L
40%
60%
t
CYCLE,L
AC Device Specifications
(continued)
Parameter
Description
Min.
Max.
Unit
120
120
10 pF
LCLK
Figure 1. LCLK Test Load Circuit
R
S
R
S
R
P
R
P
Z
CH
Z
CH
R
T
= Z
CH
R
T
= Z
CH
Measurement Point
Measurement Point
Differential
Driver
Figure 2. Equivalent Circuit
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| CY22313 | Clocks and Buffers |
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| CY2254 | CPU System Clock Generator |
| CY2255 | CPU System Clock Generator |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2212ZC-2 | 制造商:Cypress Semiconductor 功能描述: |
| CY2212ZC-2T | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| CY2212ZXC-2 | 功能描述:鎖相環(huán) - PLL Rambus Lite Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY2212ZXC-2T | 功能描述:鎖相環(huán) - PLL HI Freq PECL Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY2213 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:High-Frequency Programmable PECL Clock Generator |
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