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參數(shù)資料
| 型號(hào)： | CY2212 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 124K |
| 代理商： | CY2212 |
CY2212
Document #: 38-07466 Rev. **
Page 3 of 10
DC Electrical Specifications
State Transition Characteristics
Specifies the maximum settling time of the CLK, CLKB, and
LCLK outputs from device power-up. For V
DD
, V
DDP
, and V
DDL
any sequences are allowed to power-up and power-down the
CY2212 DRCG-Lite.
Parameter
V
DD
V
DDL
T
A
V
IL
V
IH
R
PUP
Description
Min.
3.04
1.7
0
Max.
3.56
2.1
70
0.35
Unit
V
V
°
C
V
DD
V
DD
k
Supply voltage
LCLK supply voltage
Ambient operating temperature
Input signal low voltage at pin S
Input signal high voltage at pin S
Internal pull-up resistance
0.65
10
100
AC Electrical Specifications
Parameter
f
XTAL,IN
C
IN,CMOS
Description
Min.
14.0625
Max.
18.75
10
Unit
MHz
pF
Input frequency at crystal input
[5]
Input capacitance at S pin
[6]
DC Device Specifications
Parameter
V
CM
V
X
V
COS
V
COH
V
COL
r
OUT
V
LOH
V
LOL
Description
Min.
1.35
1.25
0.4
Max.
1.75
1.85
0.7
2.1
Unit
V
V
V
V
V
V
V
Differential output common-mode voltage
Differential output crossing-point voltage
Output voltage swing (p-p single-ended)
[7]
Output high voltage
Output low voltage
Output dynamic resistance (at pins)
[8]
LCLK Output high voltage at I
OH
=
–
10 mA
LCLK Output low voltage at I
OL
= 10 mA
1.0
12
50
V
DDL
–
0.45V
0
V
DDL
0.45
From
To
Transition Latency
3 ms
Description
V
DD
/V
DDL
/V
DDP
On CLK/CLKB/LCLK Normal
Time from V
DD
/V
DDL
/V
DDP
is applied and settled to
CLK/CLKB/LCLK outputs settled
AC Device Specifications
Parameter
t
CYCLE
t
J
Description
Min.
2.5
Max.
3.33
100
140
300
400
55%
50
70
Unit
ns
ps
ps
ps
ps
t
CYCLE
ps
ps
Clock cycle time
Jitter over 1
–
6 clock cycles at 400 MHz
[9]
Jitter over 1
–
6 clock cycles at 300 MHz
[9]
Long-term jitter at 400 MHz
Long-term jitter at 300 MHz
Long-term average output duty cycle
Cycle-cycle duty cycle error at 400 MHz
Cycle-cycle duty cycle error at 300 MHz
t
JL
DC
t
DC,ERR
45%
Notes:
5.
6.
7.
8.
9.
Nominal condition with 18.75-MHz crystal.
Capacitance measured at Freq = 1 MHz, DC Bias = 0.9 V, and VAC < 100 mV.
V
COS
= V
OH
–
V
OL
.
r
=
V
/
I
. This is defined at the output pins, not at the measurement point of
Figure 3
.
Output short-term jitter specification is peak-peak and defined in
Figure 10
.
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