參數(shù)資料
型號(hào): CY2212
英文描述: Clocks and Buffers
中文描述: 時(shí)鐘和緩沖器
文件頁(yè)數(shù): 2/10頁(yè)
文件大?。?/td> 124K
代理商: CY2212
CY2212
Document #: 38-07466 Rev. **
Page 2 of 10
Pin Description
Absolute Maximum Conditions
Crystal Requirements
These are the requirements for the recommended crystal to be
used with the CY2212 DRCG Lite clock source. The crystal
type is parallel resonant. The mode is fundamental. Internal
capacitors will not be implemented in the crystal oscillator
circuit. External capacitors will be needed.
Notes:
1.
2.
3.
4.
At 25
°
C ± 3
°
C.
CL = 10 pF.
10
°
C to 75
°
C.
At X
F
± 500 kHz.
Name
VDDP
VSSP
XOUT
XIN
VDDL
LCLK
VSSL
NC
NC
VDD
VSS
CLKB
CLK
VSS
VDD
S
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
3.3V Power Supply for PLL
Ground for PLL
Reference Crystal Feedback
Reference Crystal Input
1.8V Power Supply for LCLK
LVCMOS Output, x1/2 Crystal Frequency
Ground for LCLK
No Connect (Reserved for Test Mode)
No Connect (Reserved for Test Mode)
3.3V Power Supply
Ground
Output Clock (complement), Connect to Rambus Channel
Output Clock, Connect to Rambus Channel
Ground
3.3V Power Supply
PLL Multiplier Select Input, Pull-up Resistor Internal
Parameter
V
DD,ABS
V
I, ABS
V
IL, ABS
Description
Min.
0.5
0.5
0.5
Max.
4.0
V
DD
+ 0.5
V
DDL
+ 0.5
Unit
V
V
V
Max. voltage on V
DD
, V
DDP
, or V
DDL
with respect to ground
Max. voltage on any pin with respect to ground
Max. voltage on LCLK with respect to ground
Parameter
X
F
X
FTOL
X
EQRES
X
TEMP
X
DRIVE
X
MI
X
IR
X
SAR
X
OS
Description
Min.
14.0625
15
Max.
18.75
15
100
10
1500
25.3
Unit
MHz
ppm
ppm
μ
W
mH
M
dB
dB
Frequency
Frequency Tolerance
[1]
Equivalent Resistance
[2]
Temperature Drift
[3]
Drive Level
Motional Inductance
Insulation Resistance
Spurious Attenuation Ratio
[4]
Overtone Spurious
0.01
20.7
500
3
8
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