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參數資料
| 型號： | CY2212 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數： | 6/10頁 |
| 文件大?。?/td> | 124K |
| 代理商： | CY2212 |
CY2212
Document #: 38-07466 Rev. **
Page 6 of 10
Dual-Channel Output Driver
Figure 4
shows the clock driver driving two high-impedance
channels. The purpose of the series resistors R
X
is to de-
couple the two-channels, and prevent noise from one channel
from coupling onto the second channel. With Z
CH
= 40 ohms
and the series resistor set to R
X
= 16 ohms, the channel
becomes an effective 56-ohm channel. The two channels in
parallel can be treated as a single 28-ohm channel, and all of
the external component values listed in
Table 1
can be used.
Signal Waveforms
A physical signal which appears at the pins of the device is
deemed valid or invalid depending on its voltage and timing
relations with other signals. This section defines the voltage
and timing waveforms for the input and output pins of the
CY2212. The Device Characteristics tables list the specifica-
tions for the device parameters that are defined here.
Input and Output voltage waveforms are defined as shown in
Figure 5
. Both rise and fall times are defined between the 20%
and 80% points of the voltage swing, with the swing defined
as V
H
–
V
L
. For example, the output voltage swing
V
COS
= V
OH
–
V
OL
.
The device parameters defined according to
Figure 5
are as
follows.
Figure 6
shows the definition of output crossing point. The
nominal crossing point between the complementary outputs is
defined to be at the 50% point of the DC voltage levels. There
are two crossing points defined, Vx+ at the rising edge of CLK
and Vx
–
at the falling edge of CLK. For some clock waveforms,
both Vx+ and Vx
–
might be below Vx, nom (for example, if t
CR
is larger than t
CF
). Vx is defined as the differential output
crossing point voltage.
Figure 7
shows the definition of long-term duty cycle, which is
simply the waveform high-time divided by the cycle time
(defined at the crossing point). Long-term duty cycle is the
average over many (>10,000) cycles. Short-term duty cycle is
defined in the next section. DC is defined as the output clock
long-term duty cycle.
Jitter
This section defines the specifications that relate to timing
uncertainty (or jitter) of the input and output waveforms.
Figure 8
shows the definition of long-term jitter with respect to
the falling edge of the CLK signal. Long-term jitter is the
difference between the minimum and maximum cycle times.
Equal requirements apply for rising edges of the CLK signal.
t
JL
is defined as the output long-term jitter.
Table 2. Definition of Device Parameters
Parameter
V
OH
, V
OL
V
COS
V
CM
V
IH
, V
IL
t
CR
, t
CF
t
CR
, C
F
Definition
Clock output high and low voltages
Clock output swing V
COS
= V
OH
–
V
OL
Common-mode voltage V
CM
= (V
OH
–
V
OL
)/2
Vdd LVCMOS input high and low voltages
Clock output rise and fall times
Clock output rise/fall time delta t
CR,CF
=
t
CR
–
t
CF
t
CR
t
CF
V(t)
V
OH
80%
20%
V
OL
Figure 5. Voltage Waveforms
CLK
CLKB
Vx+
Vx,nom
Vx
–
Figure 6. Crossing-point Voltage
相關PDF資料 |
PDF描述 |
|---|---|
| CY22313 | Clocks and Buffers |
| CY2250SC-1 | CPU System Clock Generator |
| CY2254 | CPU System Clock Generator |
| CY2255 | CPU System Clock Generator |
| CY2256PVC-1 | CPU System Clock Generator |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY2212ZC-2 | 制造商:Cypress Semiconductor 功能描述: |
| CY2212ZC-2T | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| CY2212ZXC-2 | 功能描述:鎖相環(huán) - PLL Rambus Lite Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY2212ZXC-2T | 功能描述:鎖相環(huán) - PLL HI Freq PECL Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY2213 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:High-Frequency Programmable PECL Clock Generator |
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