參數(shù)資料
型號(hào)： CS5526-BSZR
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 7/30頁(yè)
文件大?。?/td> 0K
描述： IC ADC 20BIT W/4BIT LATCH 20SSOP
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 20
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 12.7mW
電壓電源： 雙 ±
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 20-SSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)差分，單極；1 個(gè)差分，雙極
配用： 598-1014-ND - EVAL BOARD FOR CS5526
CS5525 CS5526
DS202F5
15
differential output voltage from the amplifier ex-
ceeds 2.8 V, the amplifier may saturate, which will
cause a measurement error.
The input voltage into the modulator must not
cause the modulator to exceed a low of 20 percent
or a high of 80 percent 1's density. The nominal full
scale input span of the modulator (from 30 percent
to 70 percent 1’s density) is determined by the
VREF voltage divided by the Gain Factor. See Ta-
ble 3 to determine if the CS5525/26 are being used
properly. For example, in the 55 mV range to de-
termine the nominal input voltage to the modulator,
divide VREF (2.5 V) by the Gain Factor (2.2727).
When a smaller voltage reference is used, the re-
sulting code widths are smaller causing the con-
verter output codes to exhibit more changing codes
for a fixed amount of noise. Table 3 is based upon
a VREF = 2.5 V. For other values of VREF, the val-
ues in Table 3 must be scaled accordingly.
Figure’s 8 and 9 illustrate the input models for the
AIN and VREF pins. The dynamic input current for
each of the pins can be determined from the models
shown and is dependent upon the setting of the CFS
(Chop Frequency Select) bit. The effective input
impedance for the AIN+ and AIN- pins remains
constant for the three low level measurement rang-
es (25 mV, 55 mV, and 100 mV). The input current
is lowest with the CFS bit cleared to logic 0.
Note: Residual noise appears in the converter’s baseband for
output word rates greater than 60 Sps if CFS is logic 0. By set-
ting CFS to logic 1, the amplifier’s chop frequency chops at
32768 Hz eliminating the residual noise, but increasing the
current. Note that C=48pF is for input current modeling only.
For physical input capacitance see ‘Input Capacitance’ spec-
ification under ‘Analog Characteristics’ on page 3.
Note:
1. The converter's actual input range, the delta-sigma's nominal full scale input, and the delta-sigma's
maximum full scale input all scale directly with the value of the voltage reference. The values in the
table assume a 2.5 V VREF voltage.
Input Range(1)
Max. Differential Output
20X Amplifier
VREF
Gain Factor
-Σ Nominal(1)
Differential Input
-Σ(1)
Max. Input
± 25 mV
2.8 V (2)
2.5V
5
± 0.5 V
± 0.75 V
± 55 mV
2.8 V (2)
2.5V
2.272727...
± 1.1 V
± 1.65 V
± 100 mV
2.8 V (2)
2.5V
1.25
± 2.0 V
± 3.0 V
± 1.0 V
-
2.5V
2.5
± 1.0 V
± 1.5 V
± 2.5 V
-
2.5V
1.0
± 2.5 V
± 5.0 V
-
2.5V
0.5
± 5.0 V
0V, VA+
Table 3. Relationship between Full Scale Input, Gain Factors, and Internal Analog Signal Limitations
AIN
25m V , 55m V , and 100m V R anges
V
≤ 25m V
i = fV
C
os
n
C = 48pF
C F S = 0 , f = 2 5 6 H z
C F S = 1 , f = 3 2 .7 6 8 kH z
AIN +
1V , 2 .5 V , and 5V R a nges
C = 32pF
i = [(V
) - (V
)] fC
n
AIN +
A IN -
AIN -
f = 32.768 kH z
Figure 8. Input models for AIN+ and AIN- pins
VR E F +
C = 16pF
VR E F -
i
= [(V R E F + ) - (V R E F -)] fC
n
f = 32.768 k H z
Figure 9. Input model for VREF+ and VREF- pins.
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