參數(shù)資料
型號(hào)： CS5526-BSZR
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 15/30頁(yè)
文件大?。?/td> 0K
描述： IC ADC 20BIT W/4BIT LATCH 20SSOP
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 20
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 12.7mW
電壓電源： 雙 ±
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 20-SSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)差分，單極；1 個(gè)差分，雙極
配用： 598-1014-ND - EVAL BOARD FOR CS5526
CS5525 CS5526
22
DS202F5
Digital Filter
The CS5525/26 have eight different linear phase
digital filters which set the output word rates
(OWRs) as stated in Table 2. These rates assume
that XIN is 32.768 kHz. Each of the filters has a
magnitude response similar to that shown in Figure
19. The filters are optimized to settle to full accura-
cy every conversion and yield better than 80 dB re-
jection for both 50 and 60 Hz with output word
rates at or below 15.0 Sps.
The converter’s digital filters scale with XIN. For
example with an output word rate of 15 Hz, the fil-
ter’s corner frequency is typically 12.7 Hz. If XIN
is increased to 64.536 kHz the OWR doubles and
the filter’s corner frequency moves to 25.4 Hz.
Output Coding
The CS5525/26 output data in binary format when
operating in unipolar mode and in two's comple-
ment when operating in bipolar mode.
The output conversion word is 24 bits, or three
bytes long, as shown in Table 5. The MSB is output
first followed by the rest of the data bits in descend-
ing order. For the CS5525 the last byte is composed
of bits D7-D4, which are always logic 1; D3-D2,
which are always logic 0; and bits D1-D0 which are
the two flag bits. For the CS5526 the last byte in-
cludes data bits D7-D4, D3-D2 which are always
logic 0 and the two flag bits.
The OF (Overrange Flag) bit is set to a logic 1 any
time the input signal is: 1) more positive than posi-
tive full scale, 2) more negative than zero (unipolar
mode), 3) more negative than negative full scale
(bipolar mode). It is cleared back to logic 0 when-
ever a conversion word occurs which is not over-
ranged.
The OD (Oscillation Detect) bit is set to a logic 1 any
time that an oscillatory condition is detected in the
modulator. This does not occur under normal operating
conditions, but may occur whenever the input to the
converters is extremely overranged. If the OD bit is set,
Figure 18. Tuning Fork Crystal Connection Diagram
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
0
A
tt
enua
ti
on
(dB)
12
3
4
5
6
7
8
9
10
11
12
13
14
15
for O W R = 15.0 H z
f1 = 47.5 H z
f2 = 65.5 H z
fS /2 = XIN /4
f1
f2
Figure 19. Filter Response
(Normalized to Output Word Rate = 1)
Sps
Table 5. Data Conversion Word
Output Conversion Data CS5525 (16 bits + flags)
Output Conversion Data CS5526 (20 bits + flags)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MSB 14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
111100
OD OF
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5
D4
D3 D2 D1 D0
MSB 18
17
16
15
14
13
12
11
10
9
8
7
6
54321
LSB
0
OD OF
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