- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗1991 > CS5526-BSZR (Cirrus Logic Inc)IC ADC 20BIT W/4BIT LATCH 20SSOP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | CS5526-BSZR |
| 寤犲晢锛� | Cirrus Logic Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 23/30闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC ADC 20BIT W/4BIT LATCH 20SSOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1,000 |
| 浣嶆暩(sh霉)锛� | 20 |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶 |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 1 |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 12.7mW |
| 闆诲闆绘簮锛� | 闆� ± |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 20-SSOP锛�0.209"锛�5.30mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 20-SSOP |
| 鍖呰锛� | 甯跺嵎 (TR) |
| 杓稿叆鏁�(sh霉)鐩拰椤炲瀷锛� | 1 鍊嬪樊鍒�锛屽柈妤碉紱1 鍊嬪樊鍒�锛岄洐妤� |
| 閰嶇敤锛� | 598-1014-ND - EVAL BOARD FOR CS5526 |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�鐣�(d膩ng)鍓嶇23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�
CS5525 CS5526
DS202F5
3
ANALOG CHARACTERISTICS (Continued)
Notes: 9. The minimum Full-scale Calibration Range (FSCR) is limited by the maximum allowed gain register
value (with margin). The maximum FSCR is limited by the
危 modulator鈥檚 1鈥檚 density range.
10. The maximum full-scale signal can be limited by saturation of circuitry within the internal signal path.
11. All outputs unloaded. All input CMOS levels.
Parameter
Min
Typ
Max
Unit
Analog Input
Common Mode + Signal on AIN+ or AIN-
Bipolar/Unipolar Mode
NBV = -1.8 to -2.5 V
Range = 25 mV, 55 mV, or 100 mV
Range = 1 V, 2.5 V, or 5 V
NBV = AGND
Range = 25 mV, 55 mV, or 100 mV
Range = 1 V, 2.5 V, or 5 V
-0.150
NBV
1.85
0.0
-
0.950
VA+
2.65
VA+
V
Common Mode Rejection
dc
50, 60 Hz
-
120
-
dB
Input Capacitance
-
10
-
pF
CVF Current on AIN+ or AIN-
(Note 5)
Range = 25 mV, 55 mV, or 100 mV
Range = 1 V, 2.5 V, or 5 V
-
100
1.2
300
-
pA
A/V
System Calibration Specifications
Full-scale Calibration Range
Bipolar/Unipolar Mode (Note 9)
25 mV
55 mV
100 mV
1 V
2.5 V
5 V
17.5
38.5
70
0.70
1.75
3.50
-
32.5
71.5
105
1.30
3.25
VA+
mV
V
Offset Calibration Range
Bipolar/Unipolar Mode
25 mV
55 mV
100 mV
(Note 10)
1 V
2.5 V
5 V
-
卤12.5
卤27.5
卤50
卤0.5
卤1.25
卤2.50
mV
V
Power Supplies
DC Power Supply Currents (Normal Mode)
IA+
ID+
INBV
-
1.65
15
475
2.2
30
700
mA
A
Power Consumption
Normal Mode
(Note 11)
Low Power Mode
Standby
Sleep
-
9.4
4.9
1.2
500
12.7
8.5
-
mW
W
Power Supply Rejection
dc Positive Supplies
dc NBV
-
95
110
-
dB
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| CS5528-ASZR | IC ADC 24BIT 8CH 24-SSOP |
| CS5529-ASZR | IC ADC 16BIT W/6BIT LATCH 20SSOP |
| CS5530-ISZR | IC ADC 24BIT 1CH W/LNA 20-SSOP |
| CS5534-ASZR | IC ADC 24BIT 4CH W/LNA 24-SSOP |
| CS5534-BSZR | IC ADC 24BIT 4CH W/LNA 24SSOP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| CS5527-000 | 鍔熻兘鎻忚堪:闆荤窔閼掑畾 HT-SCE-1K-1/8-2.0-9-CS7822 RoHS:鍚� 鍒堕€犲晢:TE Connectivity / Q-Cees 鐢�(ch菐n)鍝�:Labels and Signs 椤炲瀷: 鏉愭枡:Vinyl 椤忚壊:Blue 瀵害:0.625 in 闀峰害:1 in |
| CS5528 | 鍒堕€犲晢:CIRRUS 鍒堕€犲晢鍏ㄧū:Cirrus Logic 鍔熻兘鎻忚堪:16-bit or 24-bit, 2/4/8-channel ADCs with PGIA |
| CS5528-AP | 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪:- Bulk 鍒堕€犲晢:Cirrus Logic 鍔熻兘鎻忚堪: |
| CS5528-AS | 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 - ADC 8-Ch 24-Bit Delta Sigma Mult-range ADC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲�(ji茅)妲�(g貌u):Sigma-Delta 杞�(zhu菐n)鎻涢€熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤炲瀷:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:VQFN-32 |
| CS5528-ASZ | 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 - ADC 8-Ch 24-Bit Delta Sigma Mult-range ADC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲�(ji茅)妲�(g貌u):Sigma-Delta 杞�(zhu菐n)鎻涢€熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤炲瀷:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:VQFN-32 |
鐧�(f膩)甯冪穵鎬ラ噰璩硷紝3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�
