參數(shù)資料
型號(hào)： CS5526-BSZR
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 16/30頁(yè)
文件大?。?/td> 0K
描述： IC ADC 20BIT W/4BIT LATCH 20SSOP
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 20
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 12.7mW
電壓電源： 雙 ±
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 20-SSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)差分，單極；1 個(gè)差分，雙極
配用： 598-1014-ND - EVAL BOARD FOR CS5526
CS5525 CS5526
DS202F5
23
the conversion data bits can be completely erroneous.
The OD flag bit will be cleared to logic 0 when the
modulator becomes stable. Table 6 illustrates the out-
put coding for the CS5525/26.
Power Consumption
The CS5525/26 accommodate four power consump-
tion modes: normal, low power, standby, and sleep.
The normal mode, the default mode, is entered after a
power-on-reset and typically consumes 9.4 mW. The
low power mode is an alternate mode that reduces the
consumed power to 4.9 mW. It is entered by setting
bit D16 (the low power mode bit) in the configuration
register to logic 1. Since the converter’s noise perfor-
mance improves with increased power consumption,
slightly degraded noise or linearity performance
should be expected in the low power mode. The final
two modes are referred to as the power save modes.
They power down most of the analog portion of the
chips and stop filter convolutions. The power save
modes are entered whenever the PS/R bit and the CB
bit of the command word are set to logic 1. The par-
ticular power save mode entered depends on state of
bit D4 (the Power Save Select bit) in the configura-
tion register. If D4 is logic 0, the converters enters the
standby mode reducing the power consumption to
1.2mW. The standby mode leaves the oscillator and
the on-chip bias generator running. This allows the
converters to quickly return to the normal or low
power mode once the PS/R bit is set back to a logic 1.
If D4 in the configuration register and CB and PS/R
in the command word are set to logic 1, the sleep
mode is entered reducing the consumed power to less
than 500 W. Since the sleep mode disables the oscil-
lator, approximately a 500ms oscillator start-up delay
period is required before returning to the normal or
low power mode.
PCB Layout
The CS5525/26 should be placed entirely over an an-
alog ground plane with both the AGND and DGND
pins of the device connected to the analog plane.
Place the analog-digital plane split immediately adja-
cent to the digital portion of the chip.
The XIN pin represents a very high impedance when
used with a crystal, so care should be taken in routing
the trace from the crystal to the XIN pin to keep it as
short as possible. Stray capacitance between the CPD
pin and the XIN pin should be minimizedby keeping
the CPD pin trace away from XIN.
Note: VFS in the table equals the voltage between ground and full scale for any of the unipolar gain ranges, or the
voltage between
± full scale for any of the bipolar gain ranges. See text about error flags under overrange
conditions.
Unipolar Input
Voltage
Offset
Binary
Bipolar Input
Voltage
Two's
Complement
Unipolar Input
Voltage
Offset
Binary
Bipolar Input
Voltage
Two's
Complement
>(VFS-1.5 LSB)
FFFF
>(VFS-1.5 LSB)
7FFF
>(VFS-1.5 LSB) FFFFF
>(VFS-1.5 LSB)
7FFFF
VFS-1.5 LSB
FFFF
-----
FFFE
VFS-1.5 LSB
7FFF
-----
7FFE
VFS-1.5 LSB
FFFFF
-----
FFFFE
VFS-1.5 LSB
7FFFF
-----
7FFFE
VFS/2-0.5 LSB
8000
-----
7FFF
-0.5 LSB
0000
-----
FFFF
VFS/2-0.5 LSB
80000
-----
7FFFF
-0.5 LSB
00000
-----
FFFFF
+0.5 LSB
0001
-----
0000
-VFS+0.5 LSB
8001
-----
8000
+0.5 LSB
00001
-----
00000
-VFS+0.5 LSB
80001
-----
80000
<(+0.5 LSB)
0000
<(-VFS+0.5 LSB)
8000
<(+0.5 LSB)
00000
<(-VFS+0.5 LSB)
80000
Table 6. 5525/26 Output Coding
CS5525 16-Bit Output Coding
CS5526 20-Bit Output Coding
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