參數(shù)資料
型號(hào): CS5526-BSZR
廠商: Cirrus Logic Inc
文件頁數(shù): 6/30頁
文件大?。?/td> 0K
描述: IC ADC 20BIT W/4BIT LATCH 20SSOP
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 20
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 12.7mW
電壓電源: 雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 20-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)差分,單極;1 個(gè)差分,雙極
配用: 598-1014-ND - EVAL BOARD FOR CS5526
CS5525 CS5526
14
DS202F5
Analog Input
Figure 7 illustrates a block diagram of the analog in-
put signal path inside the CS5525/26. The front end
consists of a chopper-stabilized instrumentation am-
plifier with 20X gain and a programmable gain sec-
tion. The instrumentation amplifier is powered from
VA+ and from the NBV (Negative Bias Voltage) pin
allowing the CS5525/26 to be operated in either of
two analog input configurations. The NBV pin can
be biased to a negative voltage between -1.8 V and
-2.5 V, or tied to AGND. The choice of the operating
mode for the NBV voltage depends upon the input
signal and its common mode voltage.
For the 25 mV, 55 mV, and 100 mV input ranges, the
input signals to AIN+ and AIN- are amplified by the
20X instrumentation amplifier. For ground refer-
enced signals with magnitudes less then 100 mV, the
NBV pin should be biased with -1.8 V to -2.5 V. If
NBV is tied between -1.8 V and -2.5 V, the (Com-
mon Mode + Signal) input on AIN+ and AIN- must
stay between -0.150 V and 0.950 V to ensure prop-
er operation. Alternatively, NBV can be tied to
AGND where the input (Common Mode + Signal)
on AIN+ and AIN- must stay between 1.85 V and
2.65 V to ensure that the amplifier operates prop-
erly.
For the 1 V, 2.5 V, and 5 V input ranges, the instru-
mentation amplifier is bypassed and the input sig-
nals are directly connected to the Programmable
Gain block. With NBV tied between -1.8 V and
-2.5 V, the (Common Mode + Signal) input on
AIN+ and AIN- must stay between NBV and VA+.
Alternatively, NBV can be tied to AGND where
the input (Common Mode + Signal) on AIN+ and
AIN- pins can span the entire range between
AGND and VA+.
The CS5525/26 can accommodate full scale ranges
other than 25 mV, 55 mV, 100 mV, 1 V, 2.5 V and
5 V by performing a system calibration within the
limits specified. See the Calibration section for
more details. Another way to change the full scale
range is to increase or to decrease the voltage refer-
ence to other than 2.5 V. See the Voltage Refer-
ence section for more details.
Three factors set the operating limits for the input
span. They include: instrumentation amplifier satu-
ration, modulator 1’s density, and a lower reference
voltage. When the 25 mV, 55 mV or 100 mV range
is selected, the input signal (including the common
mode voltage and the amplifier offset voltage)
must not cause the 20X amplifier to saturate in ei-
ther its input stage or output stage. To prevent sat-
uration the absolute voltages on AIN+ and AIN-
must stay within the limits specified (refer to the
‘Analog Input’ table on page 3). Additionally, the
differential output voltage of the amplifier must not
exceed 2.8 V. The equation
ABS(VIN + VOS) x 20 = 2.8 V
defines the differential output limit, where
VIN = (AIN+) - (AIN-)
is the differential input voltage and VOS is the ab-
solute maximum offset voltage for the instrumenta-
tion amplifier (VOS will not exceed 40 mV). If the
VR EF +
D ifferen tial 4th
ord er d elta-
s igm a m o d ula tor
D ig ita l F ilter
AIN +
AIN -
Pro g ra m m a b le
Ga in
VR EF -
NBV
X2 0
Figure 7. Block Diagram of Analog Signal Path
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