- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1991 > CS5526-BSZR (Cirrus Logic Inc)IC ADC 20BIT W/4BIT LATCH 20SSOP PDF資料下載
參數(shù)資料
| 型號(hào)： | CS5526-BSZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁(yè)數(shù)： | 14/30頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 20BIT W/4BIT LATCH 20SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 20 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 12.7mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)差分，單極；1 個(gè)差分，雙極 |
| 配用： | 598-1014-ND - EVAL BOARD FOR CS5526 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)當(dāng)前第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)
CS5525 CS5526
DS202F5
21
sion. The user would then issue 8 SCLKs (with
SDI = logic 0) to clear the SDO flag. Upon the fall-
ing edge of the 8th SCLK, the SDO pin will present
the first bit (MSB) of the conversion word. 24
SCLKs (high, then low) are required to read the
conversion word from the port. The user must not
give an explicit command to read the conversion
data register when the PF bit is set to logic 1. The
data conversion word must be read before a new
command can be entered (if the SC command is
used with PF = 1).
If the CC (Continuous Conversion) command is is-
sued (CC = 1, CB =1, all other command bits = 0)
the SDO pin will go low at the completion of a con-
version. The user would then issue 8 SCLKs (with
SDI = logic 0) to clear the SDO flag. Upon the fall-
ing edge of the 8th SCLK, the SDO pin will present
the first bit (MSB) of the conversion word. 24
SCLKs (high, then low) are required to read the
conversion word from the port. The user must not
give an explicit command to read the conversion
data register when the PF bit is set to logic 1. When
operating in the continuous conversion mode, the
user need not read every conversion. If the user
does nothing after SDO falls, SDO will rise one
XIN clock cycle before the next conversion word is
available and then fall again to signal that another
conversion word is available. If the user begins to
clear the SDO flag and read the conversion data,
this action must be finished before the conversion
cycle which is occurring in the background is com-
plete if the user wants to be able to read the new
conversion data.
To exit the continuous conversion mode, issue any
valid command to the SDI input when the SDO flag
falls. If a CC command is issued to the converter
while it is performing a conversion, the filter will
restart a convolution cycle to perform a new con-
version.
Output Word Rate Selection
The WR2-WR0 bits of the configuration register
set the output conversion word rate of the convert-
ers as shown in Table 2. The word rates indicated
in the table assume a master clock of 32.768 kHz.
Upon reset the converters are set to operate with an
output word rate of 15.0 Sps.
Clock Generator
The CS5525/26 include a gate which can be con-
nected with an external crystal to provide the master
clock for the chips. They are designed to operate us-
ing a low-cost 32.768 kHz “tuning fork” type crys-
tal. The 32.768 kHz crystal should be connected as
shown in Figure 18. Lead lengths should be mini-
mized to reduce stray capacitance.
The converters will operate with an external
(CMOS compatible) clock with frequencies up to
three times the typical crystal frequency of 32.768
kHz. Figure 17 details the converter’s performance
at increased clock rates.
The 32.768 kHz crystal is normally specified as a
time-keeping crystal with tight specifications for
both initial frequency and for drift over temperature.
To maintain excellent frequency stability, these
crystals are specified only over limited operating
temperature ranges (i.e. -10 °C to +60 °C). However,
applications with the CS5525/26 don’t generally re-
quire such tight tolerances. When 32.768 kHz tuning
fork crystals are used, it is recommended that protec-
tion components, an external resistor and capacitor
as shown in Figure 18, be used.
Figure 17. High Speed Clock Performance
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CS5528-ASZR | IC ADC 24BIT 8CH 24-SSOP |
| CS5529-ASZR | IC ADC 16BIT W/6BIT LATCH 20SSOP |
| CS5530-ISZR | IC ADC 24BIT 1CH W/LNA 20-SSOP |
| CS5534-ASZR | IC ADC 24BIT 4CH W/LNA 24-SSOP |
| CS5534-BSZR | IC ADC 24BIT 4CH W/LNA 24SSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS5527-000 | 功能描述:電線鑒定 HT-SCE-1K-1/8-2.0-9-CS7822 RoHS:否 制造商:TE Connectivity / Q-Cees 產(chǎn)品:Labels and Signs 類型: 材料:Vinyl 顏色:Blue 寬度:0.625 in 長(zhǎng)度:1 in |
| CS5528 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:16-bit or 24-bit, 2/4/8-channel ADCs with PGIA |
| CS5528-AP | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cirrus Logic 功能描述: |
| CS5528-AS | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Ch 24-Bit Delta Sigma Mult-range ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5528-ASZ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Ch 24-Bit Delta Sigma Mult-range ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。