參數(shù)資料
型號(hào)： CS43L22-CNZR
廠商： Cirrus Logic Inc
文件頁數(shù)： 65/66頁
文件大?。?/td> 0K
描述： IC DAC W/HDPN & SPKR AMPS 40-QFN
標(biāo)準(zhǔn)包裝： 4,000
位數(shù)： 24
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 40-QFN（6x6）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 2 電壓，單極
采樣率（每秒）： 96k
配用： 598-1529-ND - BOARD EVAL FOR CS43L22
8
DS792F2
CS43L22
Confidential Draft
3/4/10
1.1
I/O Pin Characteristics
Input and output levels and associated power supply voltage are shown in the table below. Logic levels
should not exceed the corresponding power supply voltage.
AGND
17
Analog Ground (Input) - Ground reference for the internal analog section.
FILT+
18
Positive Voltage Reference (Output) - Filter connection for the internal sampling circuits.
VQ
19
Quiescent Voltage (Output) - Filter connection for the internal quiescent voltage.
TSTO
20,36 Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no
connection external to the pin).
AIN4A,B
AIN3A,B
AIN2A,B
AIN1A,B
21,22
23,24
25,26
29,30
Line-Level Analog Inputs (Input) - Single-ended stereo line-level analog inputs.
AFILTA,AFILTB
27,28 Anti-alias Filter Connection (Output) - Anti-alias filter connection for analog passthrough mode.
SPKR/HP
31
Speaker/Headphone Switch (Input) - Powers down the left and/or right channel of the speaker
and/or headphone outputs.
RESET
32
Reset (Input) - The device enters a low power mode when this pin is driven low.
VL
33
Digital Interface Power (Input) - Determines the required signal level for the serial audio inter-
face and host control port.
VD
34
Digital Power (Input) - Positive power for the internal digital section.
DGND
35
Digital Ground (Input) - Ground reference for the internal digital section.
MCLK
37
Master Clock (Input) - Clock source for the delta-sigma modulators.
SCLK
38
Serial Clock (Input/Output) - Serial clock for the serial audio interface.
SDIN
39
Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
LRCK
40
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on
the serial audio data line.
GND/Thermal Pad
-
Ground reference for PWM power FETs and charge pump; thermal relief pad for optimized heat
dissipation.
Power
Supply
Pin Name
I/O
Internal
Connections
Driver
Receiver
VL
RESET
Input
-
1.65 V - 3.47 V, with Hysteresis
AD0
Input
-
1.65 V - 3.47 V, with Hysteresis
SCL
Input
-
1.65 V - 3.47 V, with Hysteresis
SDA
Input/
Output
-
1.65 V - 3.47 V, CMOS/Open
Drain
1.65 V - 3.47 V, with Hysteresis
MCLK
Input
-
1.65 V - 3.47 V
LRCK
Input/
Output
Weak Pull-up
(~1 M
Ω)
1.65 V - 3.47 V, CMOS
1.65 V - 3.47 V
SCLK
Input/
Output
Weak Pull-up
(~1 M
Ω)
1.65 V - 3.47 V, CMOS
1.65 V - 3.47 V
SDIN
Input
-
1.65 V - 3.47 V
VA
SPKR/HP
Input
-
1.65 V - 2.63 V
VP
SPKR_OUTA+ Output
-
1.6 V - 5.25 V Power MOSFET
-
SPKR_OUTA- Output
-
1.6 V - 5.25 V Power MOSFET
-
SPKR_OUTB+ Output
-
1.6 V - 5.25 V Power MOSFET
-
SPKR_OUTB- Output
-
1.6 V - 5.25 V Power MOSFET
-
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