參數(shù)資料
型號(hào): CS43L22-CNZR
廠商: Cirrus Logic Inc
文件頁數(shù): 35/66頁
文件大?。?/td> 0K
描述: IC DAC W/HDPN & SPKR AMPS 40-QFN
標(biāo)準(zhǔn)包裝: 4,000
位數(shù): 24
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 40-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 40-QFN(6x6)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 2 電壓,單極
采樣率(每秒): 96k
配用: 598-1529-ND - BOARD EVAL FOR CS43L22
40
DS792F2
CS43L22
Confidential Draft
3/4/10
7.4.6
MCLK Divide By 2
Divides the input MCLK by 2 prior to all internal circuitry.
Note:
In Slave Mode, this bit is ignored when the AUTO bit (“Auto-Detect” on page 38) is disabled.
7.5
Interface Control 1 (Address 06h)
7.5.1
Master/Slave Mode
Configures the serial port I/O clocking.
7.5.2
SCLK Polarity
Configures the polarity of the SCLK signal.
7.5.3
DSP Mode
Configures a data-packed interface format for the DAC.
Notes:
1.
Select the audio word length using the AWL[1:0] bits (“Audio Word Length” on page 41).
2.
The interface format for the DAC must be set to “Left-Justified” when DSP Mode is enabled.
7.5.4
DAC Interface Format
Configures the digital interface format for data on SDIN.
Note:
Select the audio word length for Right Justified using the AWL[1:0] bits (“Audio Word Length” on
MCLKDIV2
MCLK signal into DAC
0
No divide
1
Divided by 2
Application:
76
543
21
0
M/S
INV_SCLK
Reserved
DSP
DACDIF1
DACDIF0
AWL1
AWL0
M/S
Serial Port Clocks
0
Slave (input ONLY)
1
Master (output ONLY)
INV_SCLK
SCLK Polarity
0
Not Inverted
1
Inverted
DSP
DSP Mode
0
Disabled
1
Enabled
Application:
DACDIF[1:0]
DAC Interface Format
00
Left Justified, up to 24-bit data
01
IS, up to 24-bit data
10
Right Justified
11
Reserved
Application:
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