參數(shù)資料
型號(hào)： CS43L22-CNZR
廠商： Cirrus Logic Inc
文件頁數(shù)： 25/66頁
文件大?。?/td> 0K
描述： IC DAC W/HDPN & SPKR AMPS 40-QFN
標(biāo)準(zhǔn)包裝： 4,000
位數(shù)： 24
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 40-QFN（6x6）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 2 電壓，單極
采樣率（每秒）： 96k
配用： 598-1529-ND - BOARD EVAL FOR CS43L22
DS792F2
31
CS43L22
Confidential Draft
3/4/10
4.7.1
DSP Mode
In DSP Mode, the LRCK acts as a frame sync for 2 data-packed words (left and right channel) input on
SDIN. The MSB is input on the first SCLK rising edge after the frame sync rising edge. The right channel
immediately follows the left channel.
4.8
Initialization
The CS43L22 enters a Power-Down state upon initial power-up. The interpolation and decimation filters,
delta-sigma and PWM modulators and control port registers are reset. The internal voltage reference, and
switched-capacitor low-pass filters are powered down.
The device will remain in the Power-Down state until the RESET pin is brought high. The control port is ac-
cessible once RESET is high and the desired register settings can be loaded per the interface descriptions
Once MCLK is valid, the quiescent voltage, VQ, and the internal voltage reference, FILT+, will begin power-
ing up to normal operation. The charge pump slowly powers up and charges the capacitors. Power is then
applied to the headphone amplifiers and switched-capacitor filters, and the analog/digital outputs enter a mut-
ed state. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the
MCLK/LRCK frequency ratio and normal operation begins.
4.9
Recommended Power-Up Sequence
1.
Hold RESET low until the power supplies are stable.
2.
Bring RESET high.
3.
The default state of the “Power Ctl. 1” register (0x02) is 0x01. Load the desired register settings while
keeping the “Power Ctl 1” register set to 0x01.
4.
Load the required initialization settings listed in Section 4.11.
5.
Apply MCLK at the appropriate frequency, as discussed in Section 4.6. SCLK may be applied or set to
master at any time; LRCK may only be applied or set to master while the PDN bit is set to 1.
6.
Set the “Power Ctl 1” register (0x02) to 0x9E.
7.
Bring RESET low if the analog or digital supplies drop below the recommended operating condition to
prevent power glitch related issues.
4.10
Recommended Power-Down Sequence
To minimize audible pops when turning off or placing the DAC in standby,
1.
Mute the DAC’s and PWM outputs.
2.
Disable soft ramp and zero cross volume transitions.
3.
Set the “Power Ctl 1” register (0x02) to 0x9F.
LRCK
SCLK
MS B
LS B
SDIN
HP/LINE OUTB
LS B
Le ft C h an n e l
R ight C h an n el
MS B
LS B MS B
Audio Word Length (AWL)
1/fs
HP/LINE OUTA
Figure 15. DSP Mode Format)
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