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參數(shù)資料
| 型號(hào)： | CS43L22-CNZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 51/66頁 |
| 文件大小： | 0K |
| 描述： | IC DAC W/HDPN & SPKR AMPS 40-QFN |
| 標(biāo)準(zhǔn)包裝： | 4,000 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 40-QFN（6x6） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | 96k |
| 配用： | 598-1529-ND - BOARD EVAL FOR CS43L22 |
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DS792F2
55
CS43L22
Confidential Draft
3/4/10
7.25
Limiter Attack Rate (Address 29h)
7.25.1
Limiter Attack Rate
Sets the rate at which the limiter applies digital attenuation from levels above the MAX[2:0] threshold
Note:
The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and
the DIGSFT (“Digital Soft Ramp” on page 44) and DIGZC (“Digital Zero Cross” on page 45) setting unless
the respective disable bit (“Limiter Soft Ramp Disable” on page 53 or “Limiter Zero Cross Disable” on
page 54) is enabled.
7.26
Status (Address 2Eh) (Read Only)
For all bits in this register, a “1” means the associated error condition has occurred at least once since the
register was last read. A”0” means the associated error condition has NOT occurred since the last reading
of the register. Reading the register resets all bits to 0.
7.26.1
Serial Port Clock Error (Read Only)
Indicates the status of the MCLK to LRCK ratio.
Note:
On initial power up and application of clocks, this bit will report ‘1’b as the serial port re-synchro-
nizes.
7.26.2
DSP Engine Overflow (Read Only)
Indicates the over-range status in the DSP data path.
7
6
5
432
10
Reserved
LIMARATE5
LIMARATE4
LIMARATE3
LIMARATE2
LIMARATE1
LIMARATE0
LIMARATE[5:0]
Attack Time
00 0000
Fastest Attack
11 1111
Slowest Attack
Application:
7
6
5
432
10
Reserved
SPCLKERR
DSPAOVFL
DSPBOVFL
PCMAOVFL
PCMBOVFL
Reserved
SPCLKERR
Serial Port Clock Status:
0
MCLK/LRCK ratio is valid.
1
MCLK/LRCK ratio is not valid.
Application:
DSPxOVFL
DSP Overflow Status:
0
No digital clipping has occurred in the data path after the DSP.
1
Digital clipping has occurred in the data path after the DSP.
Application:
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS43L23-CWZR | 功能描述:IC DAC W/HDPN & SPKR AMPS 40-QFN 制造商:cirrus logic inc. 系列:* 零件狀態(tài):Not For New Designs 標(biāo)準(zhǔn)包裝:6,000 |
| CS43L36-CNZ | 功能描述:IC-LOWPOWERHIGHPERFORMANCE HEADP 制造商:cirrus logic inc. 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:490 |
| CS43L41 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low Power 24-Bit, 96 kHz DAC with Volume Control |
| CS43L41-KZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CS43L42 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low Voltage,Stereo DAC With Headphone Amp |
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