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參數(shù)資料
| 型號： | CS43L22-CNZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 26/66頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC W/HDPN & SPKR AMPS 40-QFN |
| 標準包裝： | 4,000 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 40-QFN（6x6） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | 96k |
| 配用： | 598-1529-ND - BOARD EVAL FOR CS43L22 |
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32
DS792F2
CS43L22
Confidential Draft
3/4/10
4.
Wait at least 100 s.
The device will be fully powered down after this 100 s delay. Prior to the removal of the master clock
(MCLK), this delay of at least 100 s must be implemented after step 3 to avoid premature disruption
of the DAC’s power down sequence.
A disruption in the device’s power down sequence (i.e. removing the MCLK signal before this 100 s
delay) has consequences on both the headphone and PWM speaker amplifiers: The charge pump may
stop abruptly, causing the headphone amplifiers to drive the outputs up to the +VHP supply. Also, the
last state of each ‘+’ and ‘-’ PWM output terminal before the premature removal of MCLK could randomly
be held at either VP or AGND. When this event occurs, it is possible for each PWM terminal to output
opposing potentials, creating a DC source into the speaker voice coil.
The disruption of the device’s power down sequence may also cause clicks and pops on the output of
the DAC’s as the modulator holds the last output level before the MCLK signal was removed.
5.
MCLK may be removed at this time.
6.
To achieve the lowest operating quiescent current, bring RESET low. All control port registers will be
reset to their default state.
4.11
Required Initialization Settings
Various sections in the device must be adjusted by implementing the initialization settings shown below after
power-up sequence step 3. All performance and power consumption measurements were taken with the
following settings:
1.
Write 0x99 to register 0x00.
2.
Write 0x80 to register 0x47.
3.
Write ‘1’b to bit 7 in register 0x32.
4.
Write ‘0’b to bit 7 in register 0x32.
5.
Write 0x00 to register 0x00.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CS43L23-CWZR | 功能描述:IC DAC W/HDPN & SPKR AMPS 40-QFN 制造商:cirrus logic inc. 系列:* 零件狀態(tài):Not For New Designs 標準包裝:6,000 |
| CS43L36-CNZ | 功能描述:IC-LOWPOWERHIGHPERFORMANCE HEADP 制造商:cirrus logic inc. 系列:* 零件狀態(tài):在售 標準包裝:490 |
| CS43L41 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low Power 24-Bit, 96 kHz DAC with Volume Control |
| CS43L41-KZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CS43L42 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low Voltage,Stereo DAC With Headphone Amp |
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