參數(shù)資料
型號: CS43L22-CNZR
廠商: Cirrus Logic Inc
文件頁數(shù): 36/66頁
文件大?。?/td> 0K
描述: IC DAC W/HDPN & SPKR AMPS 40-QFN
標(biāo)準(zhǔn)包裝: 4,000
位數(shù): 24
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 40-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 40-QFN(6x6)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 2 電壓,單極
采樣率(每秒): 96k
配用: 598-1529-ND - BOARD EVAL FOR CS43L22
DS792F2
41
CS43L22
Confidential Draft
3/4/10
7.5.5
Audio Word Length
Configures the audio sample word length used for the data into SDIN.
Note:
When the internal MCLK/LRCK ratio is set to 125 in Master Mode, the 32-bit data width option
for DSP Mode is not valid unless SCLK=MCLK.
7.6
Interface Control 2 (Address 07h)
7.6.1
SCLK equals MCLK
Configures the SCLK signal source for Master Mode.
Note:
This bit is only valid for MCLK = 12.0000 MHz.
7.6.2
Speaker/Headphone Switch Invert
Determines the control signal polarity of the SPK/HP_SW pin.
AWL[1:0]
Audio Word Length
DSP Mode
Right Justified
00
32-bit data
24-bit data
01
24-bit data
20-bit data
10
20-bit data
18-bit data
11
16-bit data
Application:
7
6
543
2
1
0
Reserved
SCLK=MCLK
Reserved
INV_SWCH
Reserved
SCLK=MCLK
Output SCLK
0
Re-timed signal, synchronously derived from MCLK
1
Non-retimed, MCLK signal
INV_SWCH
SPK/HP_SW pin 6 Control
0
Not inverted
1
Inverted
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