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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | CS4398-CZZ |
| 寤犲晢锛� | Cirrus Logic Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 8/46闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC DAC 120DB 192KHZ W/VC 28TSSOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 50 |
| 浣嶆暩(sh霉)锛� | 24 |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶 |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 2 |
| 闆诲闆绘簮锛� | 妯℃摤鍜屾暩(sh霉)瀛� |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 340mW |
| 宸ヤ綔婧害锛� | -10°C ~ 70°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 28-TSSOP锛�0.173"锛�4.40mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 28-TSSOP |
| 鍖呰锛� | 绠′欢 |
| 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷锛� | 4 闆诲锛屽柈妤� |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 216k |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 757 (CN2011-ZH PDF) |
| 閰嶇敤锛� | 598-1155-ND - BOARD EVAL FOR CS4398 DAC |
| 鍏跺畠鍚嶇ū锛� | 598-1067-5 |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�鐣�(d膩ng)鍓嶇8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�
16
DS568F1
CS4398
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, CL =20pF)
11. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
12. Data must be held for sufficient time to bridge the transition time of CCLK.
13. For FSCK < 1 MHz.
14. CDOUT should not be sampled during this time period.
15. This time is by design and not tested.
Parameter
Symbol
Min
Max
Unit
CCLK Clock Frequency
fsclk
-6
MHz
RST Rising Edge to CS Falling
tsrs
500
-
ns
CCLK Edge to CS Falling
(Note 11)
tspi
500
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
s
CS Falling to CCLK Edge
tcss
20
-
ns
CCLK Low Time
tscl
66
-
ns
CCLK High Time
tsch
66
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
CCLK Rising to DATA Hold Time
(Note 12)
tdh
15
-
ns
Rise Time of CCLK and CDIN
(Note 13)
tr2
-100
ns
Fall Time of CCLK and CDIN
(Note 13)
tf2
-100
ns
Transition time from CCLK to CDOUT valid
tscdov
-40
ns
Time from CS rising to CDOUT high-Z
tcscdo
-20
ns
t
r2
t
f2
t dsu t dh
t
sch
t scl
CS
CCL K
CD IN
t css
t
csh
t spi
t srs
RST
CD O UT
t
scdov
t
sc do v
t cscdo
Hi-Im pedance
Figure 9. Control Port Timing - SPI Format (Read/Write)
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