7.9.1 Static DSD Detect (Static_DSD) Bit 3 Function: When set to 1 (default), the DSD" />
參數(shù)資料
型號(hào): CS4398-CZZ
廠商: Cirrus Logic Inc
文件頁數(shù): 32/46頁
文件大?。?/td> 0K
描述: IC DAC 120DB 192KHZ W/VC 28TSSOP
標(biāo)準(zhǔn)包裝: 50
位數(shù): 24
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
功率耗散(最大): 340mW
工作溫度: -10°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSSOP
包裝: 管件
輸出數(shù)目和類型: 4 電壓,單極
采樣率(每秒): 216k
產(chǎn)品目錄頁面: 757 (CN2011-ZH PDF)
配用: 598-1155-ND - BOARD EVAL FOR CS4398 DAC
其它名稱: 598-1067-5
38
DS568F1
CS4398
7.9
Misc. Control - Register 09h
7.9.1
Static DSD Detect (Static_DSD) Bit 3
Function:
When set to 1 (default), the DSD processor checks for 28 consecutive zeroes or ones and, if detected,
sends a mute signal to the DACs. The MUTEC pins will eventually go active according to the DAMUTE
register.
When set to 0, this function is disabled.
7.9.2
Invalid DSD Detect (Invalid_DSD) Bit 2
Function:
When set to 1, the DSD processor checks for greater than 24 out of 28 bits of the same value and, if de-
tected, will attenuate the data sent to the DACs. The MUTEC pins go active according to the DAMUTE
register.
When set to 0 (default), this function is disabled.
7.9.3
DSD Phase Modulation Mode Select (DSD_PM_mode) Bit 1
Function:
When set to 0 (default), the 128Fs (BCKA) clock should be input to DSD_SCLK for phase modulation
mode. (See Figure 13 on page 24)
When set to 1, the 64Fs (BCKD) clock should be input to DSD_SCLK for phase modulation mode.
7.9.4
DSD Phase Modulation Mode Enable (DSD_PM_EN) Bit 0
Function:
When set to 1, DSD phase modulation input mode is enabled and the DSD_PM_MODE bit should be set
accordingly.
When set to 0 (default), this function is disabled (DSD normal mode).
76
54
3
2
1
0
Reserved Reserved Reserved Reserved STATIC_DSD INVALID_DSD DSD_PM_MODE DSD_PM_EN
0000
1
0
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