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參數(shù)資料
| 型號： | CS4398-CZZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 13/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 120DB 192KHZ W/VC 28TSSOP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 340mW |
| 工作溫度： | -10°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電壓，單極 |
| 采樣率（每秒）： | 216k |
| 產(chǎn)品目錄頁面： | 757 (CN2011-ZH PDF) |
| 配用： | 598-1155-ND - BOARD EVAL FOR CS4398 DAC |
| 其它名稱： | 598-1067-5 |
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20
DS568F1
CS4398
4. APPLICATIONS
4.1
Grounding and Power Supply Decoupling
As with any high resolution converter, the CS4398 requires careful attention to power supply and grounding
arrangements to optimize performance. The Typical Connection Diagram shows the recommended power
arrangement with VA, VD, VLS and VLC connected to clean supplies. Decoupling capacitors should be lo-
cated as close to the device package as possible. If desired, all supply pins may be connected to the same
supply, but the recommended decoupling capacitors should still be placed on each supply pin. The AGND
and DGND pins should be tied together with solid ground plane fill underneath the converter extending out
to the GND side of the decoupling caps for VA, VD, VREF, and FILT+. This recommended layout can be
seen in the CDB4398 evaluation board and datasheet.
4.2
Analog Output and Filtering
The Cirrus Logic application note “Design Notes for a 2-Pole Filter with Differential Input” (AN48) discusses
the second-order Butterworth filter and differential to single-ended converter topology that was implemented
on the CS4398 evaluation board, CDB4398, as seen in Figure 11.
The CS4398 does not include phase or amplitude compensation for an external filter. Therefore, the DAC
system phase and amplitude response is dependent on the external analog circuitry.
Figure 11. Recommended Output Filter
4.3
The MUTEC Outputs
The AMUTEC and BMUTEC pins have an auto-polarity detect feature. The MUTEC output pins are high
impedance at the time of reset. The external mute circuitry needs to be self-biased into an active state in
order to be muted during reset. Upon release of reset, the CS4398 detects the status of the MUTEC pins
(high or low) and then selects that state as the polarity to drive when the mutes become active. The external-
bias voltage level that the MUTEC pins see at the time of release of reset must meet the “MUTEC auto de-
tect input high/low voltage” specifications as outlined in the Digital Characteristics in Section 2.
Figure 12 shows a single example of both an active-high and an active-low mute drive circuit. In these de-
signs, the pull-up and pull-down resistors have been specifically chosen to meet the input high/low threshold
when used with the MMUN2111 and MMUN2211 internal bias resistances of 10 k
.
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