5.5.2 Reading in SPI Figure 16 shows the operation of the Control P" />
參數(shù)資料
型號: CS4398-CZZ
廠商: Cirrus Logic Inc
文件頁數(shù): 20/46頁
文件大?。?/td> 0K
描述: IC DAC 120DB 192KHZ W/VC 28TSSOP
標(biāo)準(zhǔn)包裝: 50
位數(shù): 24
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
功率耗散(最大): 340mW
工作溫度: -10°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSSOP
包裝: 管件
輸出數(shù)目和類型: 4 電壓,單極
采樣率(每秒): 216k
產(chǎn)品目錄頁面: 757 (CN2011-ZH PDF)
配用: 598-1155-ND - BOARD EVAL FOR CS4398 DAC
其它名稱: 598-1067-5
DS568F1
27
CS4398
Figure 15. Control Port Timing, SPI Format (Write)
5.5.2
Reading in SPI
Figure 16 shows the operation of the Control Port in SPI format. To read to a register, bring CS low. The
first seven bits on CDIN form the chip address and must be 1001100. The eighth bit is a read/write control
(R/W), which must be high to read. The CDOUT line will then output the data from the register designated
by the MAP. To read multiple registers, keep CS low and continue providing clocks on CCLK. End the
read transaction by setting CS high. The CDOUT line will go to a high-impedance state once CS goes
high.
Figure 16. Control Port Timing, SPI Format (Read)
MAP
MSB
LSB
DATA
byte 1
byte n
R/W
MAP = Memory Address Pointer
ADDRESS
CHIP
CDIN
CCLK
CS
10 01 10 0
LS B
by te 1
b yte n
R/W
A DDRE SS
CHIP
CD IN
CC L K
CS
10 01 10 0
MS B
DATA
CDO UT
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