參數(shù)資料
型號: CS4398-CZZ
廠商: Cirrus Logic Inc
文件頁數(shù): 14/46頁
文件大?。?/td> 0K
描述: IC DAC 120DB 192KHZ W/VC 28TSSOP
標準包裝: 50
位數(shù): 24
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
功率耗散(最大): 340mW
工作溫度: -10°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSSOP
包裝: 管件
輸出數(shù)目和類型: 4 電壓,單極
采樣率(每秒): 216k
產(chǎn)品目錄頁面: 757 (CN2011-ZH PDF)
配用: 598-1155-ND - BOARD EVAL FOR CS4398 DAC
其它名稱: 598-1067-5
DS568F1
21
CS4398
Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute min-
imum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer
to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit.
Figure 12. Recommended Mute Circuitry
4.4
Oversampling Modes
The CS4398 operates in one of three oversampling modes based on the input sample rate. Single-Speed
mode supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed mode
supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed mode sup-
ports input sample rates up to 200 kHz and uses an oversampling ratio of 32x.
4.5
Master and Serial Clock Ratios
The required MCLK-to-LRCK ratio and suggested SCLK-to-LRCK ratio are outlined in Table 1. MCLK can
be at any phase in regards to LRCK and SCLK. SCLK, LRCK and SDATA must meet the phase and timing
relationships outlined in Section 2. Some common MCLK frequencies have been outlined in Table 2.
MCLK/LRCK
SCLK/LRCK
LRCK
Single-Speed
256, 384, 512, 768*, 1024*, 1152*
32, 48, 64, 96, 128
Fs
Double-Speed
128, 192, 256, 384, 512*
32, 48, 64
Fs
Quad-Speed
64
32 (16 bits only)
Fs
96
32, 48
Fs
128, 256*
32, 64
Fs
192
32, 48, 64, 96
Fs
*These modes are only available in Control Port mode by setting the appropriate MCLKDIV bit.
Table 1. Clock Ratios
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