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參數(shù)資料
| 型號： | CS4398-CZZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 19/46頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 120DB 192KHZ W/VC 28TSSOP |
| 標準包裝： | 50 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 340mW |
| 工作溫度： | -10°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電壓，單極 |
| 采樣率（每秒）： | 216k |
| 產(chǎn)品目錄頁面： | 757 (CN2011-ZH PDF) |
| 配用： | 598-1155-ND - BOARD EVAL FOR CS4398 DAC |
| 其它名稱： | 598-1067-5 |
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26
DS568F1
CS4398
5.4.1
Writing in IC Format
To communicate with the CS4398, initiate a START condition of the bus (see Figure 14.). Next, send the
chip address. The eighth bit of the address byte is the R/W bit (low for a write). The next byte is the Mem-
ory Address Pointer, MAP, which selects the register to be read or written. The MAP is then followed by
the data to be written. To write multiple registers, continue providing a clock and data, waiting for the
CS4398 to acknowledge between each byte. To end the transaction, send a STOP condition.
5.4.2
Reading in IC Format
To communicate with the CS4398, initiate a START condition of the bus (see Figure 14.). Next, send the
chip address. The eighth bit of the address byte is the R/W bit (high for a read). The contents of the reg-
ister pointed to by the MAP will be output after the chip address. To read multiple registers, continue pro-
viding a clock and issue an ACK after each byte. To end the transaction, send a STOP condition.
5.5
SPI Format
In SPI format, CS is the CS4398 chip select signal; CCLK is the Control Port bit clock; CDIN is the input
data line from the microcontroller; CDOUT is the output data line and the chip address is 1001100. CS,
CCLK,and CDIN are all inputs, and data is clocked in on the rising edge of CCLK. CDOUT is an output and
is high-impedance when not actively outputting data.
5.5.1
Writing in SPI
Figure 15 shows the operation of the Control Port in SPI format. To write to a register, bring CS low. The
first seven bits on CDIN form the chip address and must be 1001100. The eighth bit is a read/write indi-
cator (R/W), which must be low to write. The next eight bits form the Memory Address Pointer (MAP),
which is set to the address of the register that is to be updated. The next eight bits are the data that will
be placed into register designated by the MAP. To write multiple registers, keep CS low and continue pro-
viding clocks on CCLK. End the read transaction by setting CS high.
SD A
SC L
100 1 1
AD 1
R/W
Sta rt
AC K
DA T A
1-8
AC K
DAT A
1-8
ACK
Sto p
N o te : If o peratio n is a w rite, th is byte contain s th e M em o ry A ddress P o inter, M A P .
No te 1
AD 0
Figure 14. Control Port Timing, IC Format
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| CS4399-CNZR | 功能描述:HIPRFDACINTGHPDRIVR&IMPED DETCTN 制造商:cirrus logic inc. 系列:* 包裝:剪切帶（CT） 零件狀態(tài):在售 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商器件封裝:40-QFN（5x5） 標準包裝:1 |
| CS4399-CWZR | 功能描述:HIPRFDACINTGHPDRIVR&IMPED DETCTN 制造商:cirrus logic inc. 系列:* 包裝:剪切帶（CT） 零件狀態(tài):在售 安裝類型:表面貼裝 封裝/外殼:42-UFBGA，WLCSP 供應(yīng)商器件封裝:42-WLCSP 標準包裝:1 |
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