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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� CS4362-KQZ
寤犲晢锛� Cirrus Logic Inc
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 4/42闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC DAC 6CH 114DB 192KHZ 48LQFP
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渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 48-LQFP锛�7x7锛�
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鍏跺畠鍚嶇ū锛� 598-1644
12
DS257F2
CS4362
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
(For KQZ TA = -10掳C to +70掳C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC, CL =30pF)
Notes:
22. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
23. Data must be held for sufficient time to bridge the transition time of CCLK.
24. For FSCK < 1 MHz.
Parameter
Symbol
Min
Max
Unit
CCLK Clock Frequency
fsclk
-
MHz
RST Rising Edge to CS Falling
tsrs
500
-
ns
CCLK Edge to CS Falling
tspi
500
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
s
CS Falling to CCLK Edge
tcss
20
-
ns
CCLK Low Time
tscl
-ns
CCLK High Time
tsch
-ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
CCLK Rising to DATA Hold Time
tdh
15
-
ns
Rise Time of CCLK and CDIN
tr2
-
100
ns
Fall Time of CCLK and CDIN
tf2
-
100
ns
MCLK
2
-----------------
1
MCLK
-----------------
1
MCLK
-----------------
t r2
t f2
t dsu t dh
t sch
t scl
CS
CCLK
CDIN
t css
t csh
t spi
t srs
RST
Figure 4. Control Port Timing - SPI Format
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
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CS4364 鍒堕€犲晢:CIRRUS 鍒堕€犲晢鍏ㄧū:Cirrus Logic 鍔熻兘鎻忚堪:103 dB, 192 kHz 6-Channel D/A Converter
CS4364_08 鍒堕€犲晢:CIRRUS 鍒堕€犲晢鍏ㄧū:Cirrus Logic 鍔熻兘鎻忚堪:103 dB, 192 kHz 6-Channel D/A Converter
CS4364-CQZ 鍔熻兘鎻忚堪:鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒- DAC IC 24bit 6Chn DAC w/ DSD Supt&Lw-Ltnc DF RoHS:鍚� 鍒堕€犲晢:Texas Instruments 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)閲�:1 DAC 杓稿嚭绔暩(sh霉)閲�:1 杞�(zhu菐n)鎻涢€熺巼:2 MSPs 鍒嗚鲸鐜�:16 bit 鎺ュ彛椤炲瀷:QSPI, SPI, Serial (3-Wire, Microwire) 绌�(w臎n)瀹氭檪(sh铆)闁�:1 us 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:SOIC-14 灏佽:Tube
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