參數(shù)資料
型號: CS4362-KQZ
廠商: Cirrus Logic Inc
文件頁數(shù): 25/42頁
文件大小: 0K
描述: IC DAC 6CH 114DB 192KHZ 48LQFP
標準包裝: 250
位數(shù): 24
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 6
電壓電源: 模擬和數(shù)字
功率耗散(最大): 390mW
工作溫度: -10°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 托盤
輸出數(shù)目和類型: 6 電壓,單極
采樣率(每秒): 200k
產(chǎn)品目錄頁面: 757 (CN2011-ZH PDF)
其它名稱: 598-1644
DS257F2
31
CS4362
7.4
SPI Format
In SPI format, CS is the CS4362 chip select signal, CCLK is the control port bit clock, CDIN is the input data
line from the microcontroller and the chip address is 0011000. CS, CCLK and CDIN are all inputs and data
is clocked in on the rising edge of CCLK.
Note:
The CS4362 is write-only when in SPI format.
7.4.1
Writing in SPI
Figure 8 shows the operation of the control port in SPI format. To write to a register, bring CS low. The
first 7 bits on CDIN form the chip address and must be 0011000. The eighth bit is a read/write indicator
(R/W), which must be low to write. The next 8 bits form the Memory Address Pointer (MAP), which is set
to the address of the register that is to be updated. The next 8 bits are the data which will be placed into
register designated by the MAP. To write multiple registers, keep CS low and continue providing clocks
on CCLK. End the read transaction by setting CS high.
SD A
SC L
00 11 0 0
ADDR
AD 0
R/W
Sta r t
ACK
DA T A
1-8
ACK
DAT A
1-8
ACK
Sto p
N o te: If o per a tion i s a w r ite, th is b y te c on tain s the M em o ry A ddr es s P o inter , M A P .
No te 1
Figure 7. Control Port Timing, IC Format
MA P
MS B
LS B
DA T A
by t e 1
by t e n
R/ W
M A P = M e m or y A d dr es s P oi n t e r
AD D R ESS
CH I P
CD I N
CC L K
CS
00 11 00 0
Figure 8. Control Port Timing, SPI Format
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