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參數(shù)資料
| 型號(hào)： | CS4362-KQZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 24/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 6CH 114DB 192KHZ 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 6 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 390mW |
| 工作溫度： | -10°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 6 電壓，單極 |
| 采樣率（每秒）： | 200k |
| 產(chǎn)品目錄頁面： | 757 (CN2011-ZH PDF) |
| 其它名稱： | 598-1644 |
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30
DS257F2
CS4362
7. CONTROL PORT INTERFACE
The control port is used to load all the internal settings. The operation of the control port may be completely asyn-
chronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
The CS4362 has MAP auto increment capability, enabled by the INCR bit in the MAP register, which is the MSB. If
INCR is 0, then the MAP will stay constant for successive writes. If INCR is set to 1, then MAP will auto increment
after each byte is written from register 01h to 08h and then from 09h and 11h, allowing block reads or writes of suc-
cessive registers in two separate sections (the counter will not auto-increment to register 09h from register 08h).
7.1
Enabling the Control Port
On the CS4362 the control port pins are shared with stand-alone configuration pins. To enable the control
port, the user must set the CPEN bit. This is done by performing a IC or SPI write. Once the control port is
enabled, these pins are dedicated to control port functionality.
To prevent audible artifacts the CPEN bit (see Section 4.1.1) should be set prior to the completion of the
Stand-Alone power-up sequence, approximately 1024 LRCK cycles. Writing this bit will halt the Stand-Alone
power-up sequence and initialize the control port to its default settings. Note, the CP_EN bit can be set any
time after RST goes high; however, setting this bit after the Stand-Alone power-up sequence has completed
can cause audible artifacts.
7.2
Format Selection
The control port has 2 formats: SPI and IC, with the CS4362 operating as a slave device.
If IC operation is desired, AD0/CS should be tied to VLC or GND. If the CS4362 ever detects a high to low
transition on AD0/CS after power-up and after the control port is activated, SPI format will be selected.
7.3
IC Format
In IC Format, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL,
with a clock to data relationship as shown in Figure Figure 7. The receiving device should send an acknowl-
edge (ACK) after each byte received. There is no CS pin. Pin AD0 forms the partial chip address and should
be tied to VLC or GND as required. The upper 6 bits of the 7 bit address field must be 001100.
Note:
MCLK is required during all IC transactions. Please see “References” on page 40 to obtain addi-
tional information on the IC Bus specification or visit http://www.semiconductors.philips.com.
7.3.1
Writing in IC Format
To communicate with the CS4362, initiate a START condition of the bus. Next, send the chip address.
The eighth bit of the address byte is the R/W bit (low for a write). The next byte is the Memory Address
Pointer, MAP, which selects the register to be read or written. The MAP is then followed by the data to be
written. To write multiple registers, continue providing a clock and data, waiting for the CS4362 to ac-
knowledge between each byte. To end the transaction, send a STOP condition.
7.3.2
Reading in IC Format
To communicate with the CS4362, initiate a START condition of the bus. Next, send the chip address.
The eighth bit of the address byte is the R/W bit (high for a read). The contents of the register pointed to
by the MAP will be output after the chip address. To read multiple registers, continue providing a clock
and issue an ACK after each byte. To end the transaction, send a STOP condition.
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| CS4362-KQZR | 功能描述:數(shù)模轉(zhuǎn)換器- DAC IC 114dB 192kHz 6Ch DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| CS4364 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:103 dB, 192 kHz 6-Channel D/A Converter |
| CS4364_08 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:103 dB, 192 kHz 6-Channel D/A Converter |
| CS4364-CQZ | 功能描述:數(shù)模轉(zhuǎn)換器- DAC IC 24bit 6Chn DAC w/ DSD Supt&Lw-Ltnc DF RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| CS4364-CQZR | 功能描述:數(shù)模轉(zhuǎn)換器- DAC IC 24b 6Ch DAC w/DSD Supt/Lw-Ltnc DF RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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