(TA=-10掳C
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鍨嬭櫉锛� CS4362-KQZ
寤犲晢锛� Cirrus Logic Inc
鏂囦欢闋佹暩(sh霉)锛� 2/42闋�
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鍖呰锛� 鎵樼洡
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10
DS257F2
CS4362
DSD - SWITCHING CHARACTERISTICS
(TA=-10掳C to 70掳C; Logic 0 = GND; VLS = 1.8 V to 5.5 V; Logic 1 = VLS Volts; CL =30 pF)
Note:
18. Min is 4 times 64x DSD or 2 times 128x DSD, and Max is 12 times 64x DSD or 6 times 128x DSD. The
proper MCLK to DSD_SCLK ratio must be set either by the DIF registers or the M0:2 pins
Parameter
Symbol
Min
Typ
Max
Unit
Master Clock Frequency
4.096
-
38.4
MHz
MCLK Duty Cycle
(All DSD
modes)
40
50
60
%
DSD_SCLK Pulse Width Low
tsclkl
20
-
ns
DSD_SCLK Pulse Width High
tsclkh
20
-
ns
DSD_SCLK Frequency
(64x Oversam-
pled)
(128x Oversampled)
1.024
2.048
-
3.2
6.4
MHz
DSD_L / _R valid to DSD_SCLK rising setup time
tsdlrs
20
-
ns
DSD_SCLK rising to DSD_L or DSD_R hold time
tsdh
20
-
ns
sclkh
t
sclkl
t
DSD_L, DSD_R
DSD_SCLK
sdlrs
t
sdh
t
Figure 2. Direct Stream Digital - Serial Audio Input Timing
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鍙冩暩(sh霉)鎻忚堪
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