參數(shù)資料
型號: CS4362-KQZ
廠商: Cirrus Logic Inc
文件頁數(shù): 14/42頁
文件大?。?/td> 0K
描述: IC DAC 6CH 114DB 192KHZ 48LQFP
標(biāo)準(zhǔn)包裝: 250
位數(shù): 24
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 6
電壓電源: 模擬和數(shù)字
功率耗散(最大): 390mW
工作溫度: -10°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 托盤
輸出數(shù)目和類型: 6 電壓,單極
采樣率(每秒): 200k
產(chǎn)品目錄頁面: 757 (CN2011-ZH PDF)
其它名稱: 598-1644
DS257F2
21
CS4362
Selects the appropriate digital filter to maintain the standard 15
μs/50 μs digital de-emphasis filter re-
sponse at 32, 44.1 or 48 kHz sample rates. (see Figure 39)
De-emphasis is only available in Single-Speed Mode.
4.4.3
Soft Ramp-Down Before Filter Mode Change (RMP_DN)
Default = 0
0 - Disabled
1 - Enabled
Function:
A mute will be performed prior to executing a filter mode change. When this feature is enabled, this mute
is effected, similar to attenuation changes, by the Soft and Zero Cross bits in the Mode Control 3 register.
When disabled, an immediate mute is performed prior to executing a filter mode change.
Note:
For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.
4.5
Invert Control (address 05h)
4.5.1
Invert Signal Polarity (Inv_Xx)
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, these bits will invert the signal polarity of their respective channels.
4.6
Mixing Control Pair 1 (Channels A1 & B1)(address 06h)
Mixing Control Pair 2 (Channels A2 & B2)(address 09h)
Mixing Control Pair 3 (Channels A3 & B3)(address 0Ch)
4.6.1
Channel A Volume = Channel B Volume (A=B)
Default = 0
0 - Disabled
1 - Enabled
Function:
The AOUTAx and AOUTBx volume levels are independently controlled by the A and the B Channel Vol-
ume Control Bytes when this function is disabled. The volume on both AOUTAx and AOUTBx are deter-
mined by the A Channel Attenuation and Volume Control Bytes (per A-B pair), and the B Channel Bytes
are ignored when this function is enabled.
76
543
21
0
Reserved
INV_B3
INV_A3
INV_B2
INV_A2
INV_B1
INV_A1
00
000
00
0
76
543
21
0
Px_A=B
PxATAPI4
PxATAPI3
PxATAPI2
PxATAPI1
PxATAPI0
PxFM1
PxFM0
00
100
10
0
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