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| 型號： | COP8CDR9LVA8 |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 83/111頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU CMOS 8BIT 68-PLCC |
| 標(biāo)準(zhǔn)包裝： | 18 |
| 系列： | COP8™ 8C |
| 核心處理器： | COP8 |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | Microwire/Plus（SPI），UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 59 |
| 程序存儲器容量： | 32KB（32K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 包裝： | 管件 |
| 其它名稱： | *COP8CDR9LVA8 |
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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
The A/D Converter takes 15 A/D clock cycles to complete a conversion. Thus the minimum A/D
conversion time is 12.0 s when a prescaler of 16 has been selected with MCLK = 20 MHz. The 15 A/D
clock cycles needed for conversion consist of 3 cycles for sampling, 1 cycle for auto-zeroing the
comparator, 10 cycles for converting, 1 cycle for loading the result into the result registers, for stopping
and for re-initializing. The ADBSY flag provides an A/D clock inhibit function, which saves power by
powering down the A/D when it is not in use.
NOTE
The A/D Converter is also powered down when the device is in either the HALT or IDLE
modes. If the A/D is running when the device enters the HALT or IDLE modes, the A/D
powers down and then restarts the conversion from the beginning with a corrupted sampled
voltage (and thus an invalid result) when the device comes out of the HALT or IDLE modes.
5.14.3 ANALOG INPUT AND SOURCE RESISTANCE CONSIDERATIONS
Figure 5-22 shows the A/D pin model in single ended mode. The differential mode has a similar A/D pin
model. The leads to the analog inputs should be kept as short as possible. Both noise and digital clock
coupling to an A/D input can cause conversion errors. The clock lead should be kept away from the
analog input line to reduce coupling.
Source impedances greater than 3 k
on the analog input lines will adversely affect the internal RC
charging time during input sampling. As shown in Figure 5-22, the analog switch to the DAC array is
closed only during the 3 A/D cycle sample time. Large source impedances on the analog inputs may result
in the DAC array not being charged to the correct voltage levels, causing scale errors.
If large source resistance is necessary, the recommended solution is to slow down the A/D clock speed in
proportion to the source resistance. The A/D Converter may be operated at the maximum speed for RS
less than 3 k
. For RS greater than 3 k, A/D clock speed needs to be reduced. For example, with RS = 6
k
, the A/D Converter may be operated at half the maximum speed. A/D Converter clock speed may be
slowed down by either increasing the A/D prescaler divide-by or decreasing the CKI clock frequency. The
A/D minimum clock speed is 65.536 kHz.
*The analog switch is closed only during the sample time.
Figure 5-22. A/D Pin Model (Single Ended Mode)
5.15 Interrupts
5.15.1 INTRODUCTION
The device supports fourteen vectored interrupts. Interrupt sources include Timer 1, Timer 2, Timer 3,
Timer T0, Port L Wake-up, Software Trap, MICROWIRE/PLUS, USART and External Input.
All interrupts force a branch to location 00FF Hex in program memory. The VIS instruction may be used to
vector to the appropriate service routine from location 00FF Hex.
The Software trap has the highest priority while the default VIS has the lowest priority.
Each of the 13 maskable inputs has a fixed arbitration ranking and vector.
Copyright 2000–2013, Texas Instruments Incorporated
Functional Description
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