參數(shù)資料
型號： COP8CDR9LVA8
廠商： National Semiconductor
文件頁數(shù)： 69/111頁
文件大小： 0K
描述： IC MCU CMOS 8BIT 68-PLCC
標(biāo)準(zhǔn)包裝： 18
系列： COP8™ 8C
核心處理器： COP8
芯體尺寸： 8-位
速度： 20MHz
連通性： Microwire/Plus（SPI），UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 59
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 68-LCC（J 形引線）
包裝： 管件
其它名稱： *COP8CDR9LVA8
SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
PEN
PSEL1
XBIT9/
CHL1
CHL0
ERR
RBFL
TBMT
PSEL0
Bit 7
Bit 0
PEN: This bit enables/disables Parity (7- and 8-bit modes only). Read/Write, cleared on reset.
PEN = 0
Parity disabled.
PEN = 1
Parity enabled.
PSEL1, PSEL0: Parity select bits. Read/Write, cleared on reset.
PSEL1 = 0, PSEL0 = 0
Odd Parity (if Parity enabled)
PSEL1 = 0, PSEL1 = 1
Even Parity (if Parity enabled)
PSEL1 = 1, PSEL0 = 0
Mark(1) (if Parity enabled)
PSEL1 = 1, PSEL1 = 1
Space(0) (if Parity enabled)
XBIT9/PSEL0: Programs the ninth bit for transmission when the USART is operating with nine data bits
per frame. For seven or eight data bits per frame, this bit in conjunction with PSEL1 selects parity.
Read/Write, cleared on reset.
CHL1, CHL0: These bits select the character frame format. Parity is not included and is generated/verified
by hardware. Read/Write, cleared on reset.
CHL1 = 0, CHL0 = 0
The frame contains eight data bits.
CHL1 = 0, CHL0 = 1
The frame contains seven data bits.
CHL1 = 1, CHL0 = 0
The frame contains nine data bits.
CHL1 = 1, CHL0 = 1
Loopback Mode selected. Transmitter output internally looped back to receiver
input. Nine bit framing format is used.
ERR: This bit is a global USART error flag which gets set if any or a combination of the errors (DOE, FE,
PE, BD) occur. Read only; it cannot be written by software, cleared on reset.
RBFL: This bit is set when the USART has received a complete character and has copied it into the
RBUF register. It is automatically reset when software reads the character from RBUF. Read only; it
cannot be written by software, cleared on reset.
TBMT: This bit is set when the USART transfers a byte of data from the TBUF register into the TSFT
register for transmission. It is automatically reset when software writes into the TBUF register. Read only,
bit is set to “one” on reset; it cannot be written by software.
ENUR—USART RECEIVE CONTROL AND STATUS REGISTER (Address at 0BB)
DOE
FE
PE
BD
RBIT9
ATTN
XMTG
RCVG
Bit 7
Bit 0
DOE: Flags a Data Overrun Error. Read only, cleared on read, cleared on reset.
DOE = 0
Indicates no Data Overrun Error has been detected since the last time the ENUR register
was read.
DOE = 1
Indicates the occurrence of a Data Overrun Error.
FE: Flags a Framing Error. Read only, cleared on read, cleared on reset.
FE = 0
Indicates no Framing Error has been detected since the last time the ENUR register was
read.
FE = 1
Indicates the occurrence of a Framing Error.
PE: Flags a Parity Error. Read only, cleared on read, cleared on reset.
60
Functional Description
Copyright 2000–2013, Texas Instruments Incorporated
Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9
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