參數(shù)資料
型號: COP8CDR9LVA8
廠商: National Semiconductor
文件頁數(shù): 31/111頁
文件大小: 0K
描述: IC MCU CMOS 8BIT 68-PLCC
標準包裝: 18
系列: COP8™ 8C
核心處理器: COP8
芯體尺寸: 8-位
速度: 20MHz
連通性: Microwire/Plus(SPI),UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 59
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 68-LCC(J 形引線)
包裝: 管件
其它名稱: *COP8CDR9LVA8
SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
NOTE
The actual memory address of the Option Register is 7FFF (hex), however the
MICROWIRE/PLUS ISP routines require the address FFFF (hex) to be used to read the
Option Register when the Flash Memory is secured.
The entire Option Register must be programmed at one time and cannot be rewritten without first erasing
the entire last page of Flash Memory.
5.7
RESET
The device is initialized when the RESET pin is pulled low or the On-chip Brownout Reset is activated.
The Brownout Reset feature is not available on the COP8CDR9.
Figure 5-2. Reset Logic
The following occurs upon initialization:
Port A: TRI-STATE (High Impedance Input)
Port B: TRI-STATE (High Impedance Input)
Port C: TRI-STATE (High Impedance Input)
Port D: HIGH
Port E: TRI-STATE (High Impedance Input)
Port F: TRI-STATE (High Impedance Input)
Port G: TRI-STATE (High Impedance Input). Exceptions: If Watchdog is enabled, then G1 is
Watchdog output. G0 and G2 have their weak pull-up enabled during RESET.
Port L: TRI-STATE (High Impedance Input)
PC: CLEARED to 0000
PSW, CNTRL and ICNTRL registers: CLEARED
SIOR:
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
T2CNTRL: CLEARED
T3CNTRL: CLEARED
HSTCR: CLEARED
ITMR: Cleared except Bit 6 (HSON) = 1
Accumulator, Timer 1, Timer 2 and Timer 3:
RANDOM after RESET
WKEN, WKEDG: CLEARED
WKPND: RANDOM
26
Functional Description
Copyright 2000–2013, Texas Instruments Incorporated
Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9
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