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參數(shù)資料
| 型號： | CD40105BMS |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS FIFO Register(CMOS 先進先出寄存器) |
| 中文描述： | FIFO寄存器的CMOS的CMOS（先進先出寄存器） |
| 文件頁數(shù)： | 9/10頁 |
| 文件大?。?/td> | 116K |
| 代理商： | CD40105BMS |
7-1325
CD40105BMS
FIGURE 8. CD40105BMS FUNCTIONAL BLOCK DIAGRAM
FIGURE 9. EXPANSION, 4-BITS WIDE-BY-16 N-BITS LONG
FIGURE 10. TIMING DIAGRAM FOR THE CD40105BMS
CONTROL LOGIC
4 x 16
DATA
REGISTER
13
12
11
10
1
14
15
9
4
5
6
7
2
3
INPUT
BUFFERS
OUTPUT
BUFFERS
Q0
Q1
Q2
Q3
3-STATE
CONTROL
D0
D1
D2
D3
DATA-IN
READY (DIR)
SHIFT IN (SI)
MASTER
RESET (MR)
DATA-OUT
READY (DOR)
SHIFT OUT (SO)
D0
D1
D2
D3
Q0
Q1
Q2
Q3
SI
DOR
DIR MR
SO
D0
D1
D2
D3
Q0
Q1
Q2
Q3
SI
DOR
DIR MR
SO
1 0
1 1
1
1
1
1
1
1
0
0
0
0
0
0
MASTER
RESET
SHIFT IN
(DATA VALID)
SHIFT OUT
INPUT READY
(CLEAR OUT)
OUTPUT READY
(CLEAR OUT)
DATA IN (Dn)
3-STATE
(OUTPUT
ENABLE)
DATA OUT
***
(UNKNOWN)
SHIFT-OUT PULSES
HAVE NO EFFECT
≈
2
μ
s
*
SHIFT-IN PULSES
HAVE NO EFFECT
≈
2
μ
s
**
HIGH
Z
INVALID
1
0
1
1
1
0
*
AT VDD =5V - RIPPLE TIME FROM POSITION 1 TO POSITION 16
**
AT VDD = 5V - RIPPLE TIME FROM POSITION 16 TO POSITION 1
***
DATA VALID
goes to high level in advance of the DATA OUT
by maximum of 50ns at VDD = 5V, 25ns at VDD = 10V,
and 20ns at VDD = 15V for CL = 50pF and T
A
= 25
C
INPUTS
OUTPUTS
INPUTS
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CD40106 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Hex Schmitt Triggers |
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| CD40106B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:CMOS HEX SCHMITT TRIGGERS |
| CD40106BC | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Hex Schmitt Trigger |
| CD40106BC_03 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Hex Schmitt Trigger |
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