參數(shù)資料
型號(hào): CD40105BMS
廠商: Intersil Corporation
英文描述: CMOS FIFO Register(CMOS 先進(jìn)先出寄存器)
中文描述: FIFO寄存器的CMOS的CMOS(先進(jìn)先出寄存器)
文件頁數(shù): 10/10頁
文件大?。?/td> 116K
代理商: CD40105BMS
1326
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
CD40105BMS
Chip Dimensions and Pad Layout
FIGURE 11. EXPANSION, 8-BITS-WIDE-BY-16 N-BITS LONG USING CD40105BMS
SI
D0
D1
D2
D3
DIR
Q0
Q1
Q2
MRQ3
DOR
SI
D0
D1
D2
D3
DIR
Q0
Q1
Q2
MRQ3
DOR
SI
D0
D1
D2
D3
DIR
Q0
Q1
Q2
MRQ3
DOR
SI
D0
D1
D2
D3
DIR
Q0
Q1
Q2
MRQ3
DOR
SHIFT
IN
DATA OUT
READY
8 BIT
DATA
8 BIT
DATA
SHIFT
OUT
DATA IN
READY
*
MASTER
RESET
*
Pulse must be applied for cascading by 16 N bits.
Dimensions in parenthesis are in millimeters and are derived from the basic
inch dimensions as indicated. Grid graduations are in mils (10-3 inch).
METALLIZATION:
PASSIVATION:
BOND PADS:
DIE THICKNESS:
Thickness: 11k
14k
, AL.
10.4k - 15.6k
, Silane
0.004 inches X 0.004 inches MIN
0.0198 inches - 0.0218 inches
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