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參數(shù)資料
| 型號： | CD40105BMS |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS FIFO Register(CMOS 先進先出寄存器) |
| 中文描述： | FIFO寄存器的CMOS的CMOS（先進先出寄存器） |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 116K |
| 代理商： | CD40105BMS |
7-1317
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
CD40105BMS
CMOS FIFO Register
Description
CD40105BMS is a low-power first-in-first-out (FIFO) “elastic”
storage register that can store 16 4-bit words. It is capable of
handling input and output data at different shifting rates. This
feature makes it particularly useful as a buffer between asyn-
chronous systems.
Each word position in the register is clocked by a control flip-
flop, which stores a marker bit. A “1” signifies that the posi-
tion’s data is filled and a “0” denotes a vacancy in that posi-
tion. The control flip-flop detects the state of the preceding
flip-flop and communicates its own status to the succeeding
flip-flop. When a control flip-flop is in the “0” state and sees a
“1” in the preceding flip-flop, it generates a clock pulse that
transfers data from the preceding four data latches into its
own four data latches and resets the preceding flip-flop to
“0”. The first and last control flip-flops have buffered outputs.
Since all empty locations “bubble” automatically to the input
end, and all valid data ripple through to the output end, the
status of the first control flip-flop (DATA-IN READY) indicates
if the FIFO is full, and the status of the last flip-flop (DATA-
OUT READY) indicates if the FIFO contains data. As the
earliest data are removed from the bottom of the data stack
(the output end), all data entered later will automatically
propagate (ripple) toward the output.
Loading Data
- Data can be entered whenever the DATA-IN
READY (DIR) flag is high, by a low to high transition on the
SHIFT-IN (SI) input. This input must go low momentarily
before the next word is accepted by the FIFO. The DIR flag
will go low momentarily, until that data have been transferred
to the second location. The flag will remain low when all 16-
word locations are filled with valid data, and further pulses
on the SI input will be ignored until DIR goes high.
Features
4 Bits x 16 Words
High Voltage Type (20V Rating)
Independent Asynchronous Inputs and Outputs
3-State Outputs
Expandable in Either Direction
Status Indicators on Input and Output
Reset Capability
Standardized Symmetrical Output Characteristics
100% Tested for Quiescent Current at 20V
5V, 10V and 15V Parametric Ratings
Maximum Input Current of 1
μ
A at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25
o
C
Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
Bit Rate Smoothing
CPU/Terminal Buffering
Data Communications
Peripheral Buffering
Line Printer Input Buffers
Auto Dialers
CRT Buffer Memories
Radar Data Acquisition
December 1992
File Number
3353
Continued on next page
Pinout
CD40105BMS
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
3 - STATE
CONTROL
DIR
SI
D0
D1
D2
VSS
D3
VDD
DOR
Q0
Q1
Q2
Q3
MR
SO
Functional Diagram
13
12
11
10
14
2
Q0
Q1
Q2
Q3
DATA-OUT
READY
DATA-IN
READY
4
5
6
7
3
15
D0
D1
D2
D3
SHIFT IN
SHIFT OUT
1
9
3-STATE
CONTROL
MASTER
RESET
VDD = 16
VSS = 8
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