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CB65000 SERIES
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The test time and cost for ASIC testing increases exponentially as the complexity and size of the ASIC grows.
Using a design-for-testability methodology allows large, more complex ASICs to be efficiently and economically
tested.
At system level, STMicroelectronics fully supports IEEE 1149.1; the I/O structure utilized in this family is com-
pletely compatible. Several types of core scan cells are provided in the CB55000 Series library. Examples in-
clude FDxS/FJKxS edge sensitive and LDxS level sensitive cells. Non-overlapping clock generator macros are
also available.
Test coverage and reliability are further supported by IDDQ (quiescent current) testing; all blocks are designed
to be “IDDQable” so that anomalous leakage due to metal bridging and dielectric defects can be screened using
proper set of vectors extracted from the test patterns.
For parametric and lddq testing, the I/O cells contain a dedicated test interface as described previously (see
Section 3.4 ‘I/O Test Interface’ on page 6).
DESIGN FOR TESTABILITY
6
ELECTRICAL SPECIFICATION
Table 2. General Interface Electrical Characteristics
Note 1: Human Body Model
6.1 3.3V I/O specifications
Table 3. LVTTL DC Input Specification (3V < vdd3 < 3.6V)
Table 4. LVTTL DC Output Specification (3V < vdd3 < 3.6V)
Note 1: X is source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
Note
Vdd
Core Power Supply Voltage
1.55
1.8
1.95
V
Vdd3
I/O Power Supply Voltage
3
3.3
3.6
V
Tj
Operating Junction Temperature
-40
25
125
°C
I latchup
I/O Latch-Up Current
200
mA
Vesd
Electrostatic Protection
Leakage < 1u
4000
V
1
Parameter
Test Conditions
Min
Typ
Max
Unit
Vil
Low Level Input Voltage
0.8
V
Vih
High Level Input Voltage
2
V
Vhyst
Schmitt Trigger Hysteresis
0.4
V
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
Note
Vol
Low Level Output Voltage
Iol = XmA
0.2
V
1
Voh
High Level Output Voltage
Ioh = -XmA
2.8
V
1