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參數(shù)資料
| 型號(hào)： | CB65000 |
| 英文描述： | HCMOS8D 0.18MICRON STANDARD CELLS FAMILY |
| 中文描述： | HCMOS8D 0.18MICRON標(biāo)準(zhǔn)單元家庭 |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大?。?/td> | 566K |
| 代理商： | CB65000 |
1/12
CB65000 Series
March 2002
FEATURE
I
0.18micron drawn, six layers of metal connected
by fully stackable vias and contacts, Shallow
Trench Isolation, low resistance, salicided
active areas and gates. Deep UV lithography.
I
1.8 V optimized High Performance and Low
Leakage transistors with 3.3 V I/O and supply
interface capability.
I
Average gate density: 85K/mm
2
, plus low power
consumption of 30nanoWatt/Gate/MHz/
Stdload.
I
Two input NAND delay of 35ps with High
Performane transistor and 60ps with Low
Leakage transistor.
I
Library available in commercial, industrial and
military temperature range. Power supply
ranging from 1.2V and 1.95V for Core
(according to JESD 8-7 specification) and
between 3.0V and 3.6V for I/Os (alligned with
JESD 8-A specification).
I
Broad I/O functionality including:
I
Low Voltage CMOS.
I
Low Voltage TTL,HSTL, SSTL.
I
AGP 2X and 4X, USB, PCI, LVDS I/O interfaces
are also available.
I
Drive capability up to 8 mA per buffer with slew
rate control, current spike suppression
impedance matching, and process
compensation capability to reduce delay
variation.
I
Designs easily portable from previous
generations of CB55000 with an average factor
2 density increase, 30% speed improvement
I
and 2.5 power reduction at respective nominal
voltages.
I
I
Generators to support Single Port, Dual port
and multiple Port RAM, and ROMs with BIST
options.
I
Extensive embedded function library including
ST DSP and micro-cores, third-party IPs,
Synopsys and Mentor Inventra synthetic
libraries ideally suited for complete System On
Chip fast integration .
I
Embedded DRAM Capability
I
80
μ
m pitch linear and 50
μ
m staggered pad
libraries.
I
Fully independent power and ground
configuration for core and I/Os supported.
I
I/O ring capability up to 1500 pads.
I
Latch-up trigger current > ± 500 mA. ESD
protection above 4 kV in H.B.M.
I
Oscillators and PLLs for wide frequency
spectrum.
I
Broad range of more than 600 SSI cells.
I
Design for test features including IEEE 1149.1
JTAG Boundary Scan architecture.
I
Synopsys, Cadence and Mentor based design
systems with interface from multiple
workstations.
I
Broad range of packaging solutions, including
PBGA, LBGA, SBGA, HPBGA, TQFP, PQFP,
PLCC up to 1000 pins with enhanced power
dissipation options.
I
1.25 GigaHertzGigabit DLL technique.
CB65000 Super Integration
Cost Effective Product
I
Architecture partitioning
I
Trouble-free integration
I
Application-specific
Your Product is Unique
I
User specified cell integration
I
Design confidentiality
I
IP fully re-usable
HCMOS8D 0.18
μ
m Standard Cells Family
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