參數(shù)資料
型號: CB65000
英文描述: HCMOS8D 0.18MICRON STANDARD CELLS FAMILY
中文描述: HCMOS8D 0.18MICRON標(biāo)準(zhǔn)單元家庭
文件頁數(shù): 5/12頁
文件大?。?/td> 566K
代理商: CB65000
5/12
CB65000 SERIES
3
The CB55000 library is organized into three categories:
– SSI cell library
– I/O cell library
– Macrofunctions
LIBRARY
3.1 SSI Cell Library Overview
The design of the CB65000 family has been optimized to allow extremely high density, high speed and low pow-
er designs. For these reasons, a wide range of cells with different ranges of driving capabilities are available in
the library.
The library cells have been optimized in terms of functional and electrical parameters, in order to have:
– Good balancing
– Maximum speed
– Optimum threshold voltage
– Symmetric V
dd
/V
ss
noise margins
– Minimum power-speed value
The geometrical aspect of the cells is configured to allow an extremely dense design, fully exploiting the features
of the Place and Route tool in terms of horizontal and vertical routing grids. For Place and Route, up to six layers
of metal are utilized; the firsts four layers fully available for signal routing, while the fifth and sixth to power dis-
tribution, clock bussing and routing.
Figure 5. NR2 and F/F examples from CB65000
3.2 Core Logic
The propagation delays shown in CB65000 data book are given for worst case processing at 1.55V and 125°C
and will be provided in the design while power data are referred to a fast process model at 1.95V and -40°C.
However, there are additional factors that affect the delay characteristics of the cells. These include: loading
due to fanout and interconnect routing, supply voltage, junction temperature of the device, processing tolerance
and input signal transition time.
Prior to physical layout, the design system can estimate the delays associated with any critical path. The impact
of the placement and routing can be accurately RC back-annotated from the layout for final simulations of critical
timing. The median effects on the cells delay of junction temperature (Kt coefficient) and supply voltage (Kv co-
efficient) are extracted from real Silicon data.
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