參數(shù)資料
型號: CB65000
英文描述: HCMOS8D 0.18MICRON STANDARD CELLS FAMILY
中文描述: HCMOS8D 0.18MICRON標(biāo)準(zhǔn)單元家庭
文件頁數(shù): 3/12頁
文件大?。?/td> 566K
代理商: CB65000
3/12
CB65000 SERIES
1
The CB65000 standard cell series uses a high performance, low-voltage, 0.18
μ
m drawn, six metal levels, high
density and high speed HCMOS8D process.
With an average routed gate density of 85,000 gates/mm
2
, the CB65000 family allows the integration of up to
30 million equivalent gates and is ideal for high-complexity or high-performance devices for computer, telecom-
munication and consumer products.
With a gate delay of 35 ps with High Performance transistor and 60 ps with Low Leakage transistor (for a 2-input
NAND gate at fan-out 1), the library meets the most demanding speed requirements in telecommunication and
computer application designs today.
Optimized for 1.8 V operation, the library features a power consumption of less than 35 nW/Gate/MHz (High
Performance; fan-out=1) and 25 nW/Gate/MHz (Low Leakage; fan-out=1) at 1.8 V.
The I/O buffers can be fully configured for both 1.8 V and 3.3 V interface options, with several high speed buffer
types available. These include: low voltage differential (LVDS) I/Os, PCI, AGP, USB, LVTTL, LVCMOS and SSTL.
The pad pitch down to 50
μ
m, in a staggered arrangement, meets the requirements of high pin-count devices
which tend to become pad-limited at such library densities. For very high pin-count ICs, advanced solutions such
as Ball Grid Array packages are available.
New packaging solutions using a flip-chip approach are currently being developed.
GENERAL DESCRIPTION
Figure 2. HCMOS8D Front end cross section
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