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參數(shù)資料
| 型號(hào)： | CB65000 |
| 英文描述： | HCMOS8D 0.18MICRON STANDARD CELLS FAMILY |
| 中文描述： | HCMOS8D 0.18MICRON標(biāo)準(zhǔn)單元家庭 |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大小： | 566K |
| 代理商： | CB65000 |
CB65000 SERIES
8/12
4
STMicrolectronics (STM) ASIC design flow is intended for high performance, high complexity submicron ASIC
designs. 3
rd
parties tools from leading EDA vendors such as Synopsys, Cadence, Mentor Graphics and STM
proprietary systems are integrated into a framework free design environment that efficiently supports all design
phases.
A hierarchical design methodology with a FastLoop, between floorplanning timing-driven placement and syn-
thesis/static timing analysis, guarantees a fast timing prediction and closure after routing.
Other features such as hierarchical Clock tree synthesis, advanced test methodology, formal verification, 3D
parasitic extraction, Crosstalk analysis, IP-reuse, qualifies the STM ASIC design flow as one of the industry's
leading solutions for today's and tomorrow's complex designs.
DESIGN METHODOLOGY
Figure 6.
Functional & Timing Specification
HDL Description & Checks
Behavioural Simulation
Preliminary RTL Floorplan
Synthesis / STA
Floorplan
Physical Synthesis
SCAN Ordering and Routing
Verification
STA
Gate Level Full Timing Simulation
Functional / Formal Verification
Clock Tree Synthesis
Routing - Optimization
Parasitic Extraction
Final Verification
STA
Gate Level Full Timing Simulation
Functional / Formal Verification
DRC / LVS
Prototype Fabrication
Scan Insertion
ATPG
IDDQ
Testing
Final Fault
Analysis
Test Vectors
&
Final Test Program
Generation
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| CB650-12-3Y | 制造商:Panduit Corp 功能描述:Lug Terminal 117.6mm 50.8mm 制造商:Panduit Corp 功能描述:LUG TERM 600-1000AWG 117.6MM 50.8MM - Bulk |
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