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參數(shù)資料
| 型號(hào)： | CB65000 |
| 英文描述： | HCMOS8D 0.18MICRON STANDARD CELLS FAMILY |
| 中文描述： | HCMOS8D 0.18MICRON標(biāo)準(zhǔn)單元家庭 |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大?。?/td> | 566K |
| 代理商： | CB65000 |
CB65000 SERIES
4/12
2
The advanced HCMOS8D transistor architecture: at 0.18
μ
m, very thin gate oxide: 35 Amstrong, optimized
threshold voltages and salicided source, drain, and gate leads to intrinsically high performances in both
N channel and P channel driving currents.
The major scaling factor is obtained through deep UV lithography at most masking levels, making sub-micron
pitch a reality.
Further integration in the process front-end comes from the use of the Shallow Trench Isolation process be-
tween active regions, both improving density and planarity of transistors. In order to allow full utilization of such
transistor density, up to 6 levels of metal are made available for routing.
The local interconnection level made in Tungsten, allows short interconnection at silicon layer improving mem-
ory and cell density., while all the six metal levels are of low resistivity aluminum for long range interconnection
and power distribution.
TECHNOLOGY OVERVIEW
Figure 3. HCMOS8D Local Interconnect
The thick inter-level dielectric is completely planarized by Chemical Mechanical Polishing, which provides de-
fect-free isolation between stripes within the same as well as between different levels.
Usage of Tungsten plugs at contacts and vias allows extremely dense and reliable interconnection between
metal layers. These vias and contacts are fully stackable, providing a direct vertical electrical connection from
the active level up to the sixth metal level. This efficient interconnect scheme makes routing fast and easy, as
well as having a very positive impact on high gate count, random-logic blocks density and routability.
The combination of both high drive and dense transistors, easily interconnected with up to six fine-pitch metal
levels and isolated by thick and low K dielectric leads to an optimum gate density, with low parasitic resistance
and capacitance. This results in very short interconnected gate delay and minimized power consumption.
Figure 4.
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