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參數(shù)資料
| 型號： | busmux |
| 廠商： | Altera Corporation |
| 英文描述： | Parameterized Multiplexer(參數(shù)確定的多路復(fù)用器) |
| 中文描述： | 參數(shù)復(fù)用器（參數(shù)確定的多路復(fù)用器） |
| 文件頁數(shù)： | 39/48頁 |
| 文件大?。?/td> | 293K |
| 代理商： | BUSMUX |
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34
Altera Corporation
Storage Functions
lpm_shiftreg
Parameterized Shift Register
Ports
Name
Type
Required
Description
sclr
Input
No
Synchronous clear input. If both
sset
and
sclr
are used and both are
asserted,
sclr
is dominant. The
sclr
input affects the output
q[]
values
before polarity is applied to the ports.
Synchronous set input. Sets
q[]
outputs to the value specified by
LPM_SVALUE
, if that value is present, or sets the
q[]
outputs to all 1s. If both
sset
and
sclr
are used and both are asserted,
sclr
is dominant. The
sset
input affects the output
q[]
values before polarity is applied to the ports.
Serial shift data input. At least one of the
data[]
,
aset
,
aclr
,
sset
,
sclr
,
and/or
shiftin
ports must be used.
Synchronous parallel load. High (1): load operation; low (0): shift operation.
Default is low (0) shift operation. For parallel load operation,
load
must be
high (1) and
enable
must be high or unconnected.
Data input to the shift register. This port is
LPM_WIDTH
wide. At least one of
the
data[]
,
aset
,
aclr
,
sset
,
sclr
and/or
shiftin
ports must be used.
Positive-edge-triggered clock. Default = 1.
Clock enable input. The shift options also use the
enable
input for the clock
enable. For serial operation, both
shiftin
and
enable
must be high.
Asynchronous clear input. If both
aset
and
aclr
are used and both are
asserted,
aclr
is dominant. The
aclr
input affects the output
q[]
values
before polarity is applied to the ports.
Asynchronous set input. Sets
q[]
outputs to the value specified by
LPM_AVALUE
, if that value is present, or sets the
q[]
outputs to all 1s. If both
aset
and
aclr
are used and both are asserted,
aclr
is dominant. The
aset
input affects the output
q[]
values before polarity is applied to the ports.
Serial shift data output. This port is
LPM_WIDTH
wide. Either
q[]
or
shiftout
or both must be used.
Data output from the shift register. This port is
LPM_WIDTH
wide. Either
q[]
or
shiftout
or both must be used.
sset
Input
No
shiftin
Input
No
load
Input
No
data[]
Input
No
clock
Input
Input
Yes
No
enable
aclr
Input
No
aset
Input
No
shiftout
Output
No
q[]
Output
No
sclr
sset
shiftin
load
data[]
clock
enable
LPM_SHIFTREG
LPM_AVALUE=
LPM_DIRECTION=
LPM_SVALUE=
LPM_WIDTH=
q[]
a
a
shiftout
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