參數(shù)資料
型號(hào): BU-64743G8-200
廠商: DATA DEVICE CORP
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80
封裝: 22.35 X 22.35 MM, 3.30 MM HEIGHT, CERAMIC, QFP-80
文件頁數(shù): 67/93頁
文件大?。?/td> 585K
代理商: BU-64743G8-200
7
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
to RT mode with the Busy bit set. The interrupt status queue and
50% rollover interrupt features are also included as improve-
ments to the Mark3's Monitor architecture.
To minimize board space and "glue" logic, the Mini-ACE Mark3
terminals provide the same wide choice of host interface config-
urations as the ACE, Mini-ACE (Plus) and Enhanced Mini-ACE.
This includes support of interfaces to 16-bit or 8-bit processors,
memory or port type interfaces, and multiplexed or non-multi-
plexed address/data buses. In addition, with respect to
ACE/Mini-ACE (Plus), the worst case processor wait time has
been significantly reduced. For example, assuming a 16 MHz
clock, this time has been reduced from 2.8 s to 632 ns for read
accesses, and to 570 ns for write accesses.
The Mini-ACE Mark3 series terminals operate over the full military
temperature range of -55 to +125°C and are available screened to
MIL-PRF-38534C. The terminals are ideal for military and industrial
processor-to-1553 applications powered by 3.3 volts only.
MICRO-ACE-TE IN SIMPLE SYSTEM RT (SSRT) MODE
The Micro-ACE-TE with 4K RAM (BU-64843B8), MIL-STD-1553
terminal can provide a complete interface between a simple sys-
tem and a MIL-STD-1553 bus when configured as an SSRT.
These terminals integrate dual transceiver, protocol logic, and a
FIFO memory for received messages in a 324-ball BGA. The
internal architecture is identical to that of the original BU-
61703/61705 Simple System RT (SSRT).
The SSRT configured Micro-ACE-TE incorporates a built-in self-
test (BIT). This BIT, which is processed following power turn-on
or after receipt of an Initiate self-test mode command, provides
a comprehensive test of the encoders, decoders, protocol, trans-
mitter watchdog timer, and protocol section. The SSRT config-
ured, Micro-ACE-TE also includes an auto-configuration feature.
The Micro-ACE-TE when configured as an SSRT is ideal for
munitions stores and other simple systems that do not require a
microprocessor. To streamline the interface to simple systems it
includes an internal 32-word FIFO for received data words. This
serves to ensure that only complete, consistent blocks of vali-
dated data words are transferred to a system.
Detailed SSRT configuration information can be found in
Application Note AN/B-37.
TEST COMPONENTS
Daisy chain mechanical samples of the Micro-ACE-TE, 324-ball
BGA (BU-64863B8-600) are available. These are used to verify
both the electrical and mechanical integrity of the solder joints
between the BGA package and the board. Ball pairs are inter-
nally wired so that the user can test for electrical continuity
between balls. Refer to TABLE 70 for interconnection details.
Although these units are inert, they are fully populated with silicon
die so that they closely match the thermal and mechanical charac-
teristics of standard production units. Internal daisy chain intercon-
nections are made by copper PWB traces.
TRANSCEIVERLESS "COMPATIBLE" VERSION OF
MICRO-ACE-TE
All versions of the Micro-ACE-TE, 324-ball BGA are transceiver-
less "Compatible". These devices contain fully functional, dual-
redundant, MIL-STD-1553 transceivers with internal / intermedi-
ate connections brought out to balls. These intermediate con-
nections allow devices to be used in transceiverless mode for
direct interfacing to MIL-STD-1773 (fiber optic) transceivers.
Mandatory Additional Connections (See TABLE 59) are required
if these devices are not utilized in their transceiverless mode.
BU-61860E3 +5.0V -ACE (MICRO-ACE) &
TRANSFORMER EVALUATION BOARD
The BU-61860E3 board is intended to support customers who
are interested in electrically connecting and evaluating the per-
formance of +5.0V Enhanced Mini-ACE and/or +5.0V -ACE
series of products. The user will be able to quickly perform func-
tional tests and run their system software utilizing this relatively
small (2.0" x 2.5") evaluation board.
The BU-61860E3 (see FIGURE 19) consists of a PC board incor-
porating a +5.0V -ACE (BU-61860B3, BC / RT / MT with 64K x
17 RAM), necessary decoupling capacitors, and associated isola-
tion transformers. The MIL-STD-1760 outputs are user config-
urable as either Stub (transformer) or Direct coupling. The board
supports the signal fan-out (see TABLE 72) of the +5.0V -ACE to
112 pins subdivided into (4) dual inline, berg type pin rows. These
pins (0.025" square max) and their row placement adhere to stan-
dard 0.100" vector board spacing.
BU-64863E8 MINI-ACE MARK3 (+3.3V) &
TRANSFORMER EVALUATION BOARD
The BU-64863E8 board is intended to support customers who
are interested in electrically connecting and evaluating the per-
formance of the +3.3V Mini-ACE Mark3 and/or +3.3V Micro-
ACE-TE series of products. The user will be able to quickly per-
form functional tests and run their system software utilizing this
relatively small (2.0" x 2.5") evaluation board.
The BU-64863E8 (see FIGURE 20) consists of a PC board incor-
porating a +3.3V Mini-ACE Mark3 (BU-64863G8, BC / RT / MT
with 64K x 17 RAM), necessary decoupling capacitors, and asso-
ciated isolation transformers. The MIL-STD-1553 outputs have
been factory configured for Stub (transformer) coupling. The
board supports the signal fan-out (see TABLE 71) of the +3.3V
Mini-ACE Mark3 to 112 pins subdivided into (4) dual inline, berg
type pin rows. These pins (0.025" square max) and their row
placement adhere to standard 0.100" vector board spacing.
TRANSCEIVERS
The transceivers in the Mini-ACE Mark3 series terminals are fully
monolithic, requiring only a +3.3 or 5.0 volt power input. The trans-
mitters are voltage sources, providing improved line driving capa-
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