參數(shù)資料
型號(hào)： BU-64743G8-200
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80
封裝： 22.35 X 22.35 MM, 3.30 MM HEIGHT, CERAMIC, QFP-80
文件頁數(shù)： 60/93頁
文件大?。?/td> 585K
代理商： BU-64743G8-200
63
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
TABLE 62. PROCESSOR INTERFACE CONTROL (CONT.)
SIGNAL NAME
DESCRIPTION
BU-64840B3
BU-64860B3
BALL
BU-64743B8
BU-64843B8
BU-64863B8
BALL
POL_SEL (I) /
DTACK (O)
N9
Data Transfer Acknowledge or Polarity Select.
In 16-bit buffered mode, if POL_SEL is connected to logic "1", RD/WR should be
asserted high (logic "1") for a read operation and low (logic "0") for a write opera-
tion. In 16-bit buffered mode, if POL_SEL is connected to logic "0", RD/WR should
be asserted low (logic "0") for a read operation and high (logic "1") for a write
operation.
In 8-bit buffered mode (TRANSPARENT/ BUFFERED = "0" and 16/8 = "0"),
POL_SEL input signal used to control the logic sense of the MSB/LSB signal. If
POL_SEL is connected to logic "0", MSB/LSB should be asserted low (logic "0")
to indicate the transfer of the least significant byte and high (logic "1") to indicate
the transfer of the most significant byte. If POL_SEL is connected to logic "1",
MSB/LSB should be asserted high (logic "1") to indicate the transfer of the least
significant byte and low (logic "0") to indicate the transfer of the most significant
byte.
In transparent mode, active low output signal (DTACK) used to indicate accep-
tance of the processor/RAM interface bus in response to a data transfer grant
(DTGRT). Mark3 RAM transfers over A15-A0 and D15-D0 will be framed by the
time that DTACK is asserted low.
V8
TRIG_SEL (I) /
MEMENA_IN (I)
L11
Memory Enable or Trigger Select input.
In 8-bit buffered mode, input signal (TRIG-SEL) used to select the order in which
byte pairs are transferred to or from the Mark3 by the host processor. In the 8-bit
buffered mode, TRIG_SEL should be asserted high (logic 1) if the byte order for
both read operations and write operations is MSB followed by LSB. TRIG_SEL
should be asserted low (logic 0) if the byte order for both read operations and
write operations is LSB followed by MSB.
This signal has no operation in the 16-bit buffered mode (it does not need to be
connected).
In transparent mode, active low input MEMENA_IN, used as a Chip Select (CS)
input to the Mark3's internal shared RAM. If only internal RAM is used, should be
connected directly to the output of a gate that is OR'ing the DTACK and IOEN out-
put signals.
N17
MEM / REG(I)
C11
Memory/Register.
Generally connected to either a CPU address line or address decoder output.
Selects between memory access (MEM/REG = "1") or register access (MEM/REG
= "0").
A6
BALL GRID ARRAY PACKAGE - SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS (CONT.)
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