參數(shù)資料
型號(hào)： BU-64743G8-200
廠商： DATA DEVICE CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80
封裝： 22.35 X 22.35 MM, 3.30 MM HEIGHT, CERAMIC, QFP-80
文件頁(yè)數(shù)： 35/93頁(yè)
文件大?。?/td> 585K
代理商： BU-64743G8-200
40
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
CLOCK IN
VALID
t7
t3
t8
t11
t13
t15
VALID
t10
t4
t9
t12
t19
;
;;
VALID
t16
t17
SELECT
(Note 2,7)
(Note 2)
(Note 3,4,7)
(Note 4,5)
STRBD
MEM/REG
RD/WR
IOEN
(Note 2,6)
(Note 6)
(Note 7,8,9)
READYD
A15-A0
D15-D0
;
;;
;;;
;;
t5
t1
t2
t6
t14
t18
FIGURE 13. CPU READING RAM / REGISTER (16-BIT BUFFERED, NONZERO WAIT)
NOTES:
1.
For the 16-bit buffered nonzero wait configuration, TRANSPARENT/BUFFERED must be connected to logic "0". ZERO_WAIT and DTREQ / 16/8
must be connected to logic "1". The inputs TRIGGER_SEL and MSB/LSB may be connected to either Vcc or ground.
2.
SELECT and STRBD may be tied together. IOEN goes low on the first rising CLK edge when SELECT STRBD is sampled low (satisfying t1)
and the Mark3’s protocol/memory management logic is not accessing the internal RAM. When this occurs, IOEN goes low, starting the transfer
cycle. After IOEN goes low, SELECT may be released high.
3.
MEM/REG must be presented high for memory access, low for register access.
4.
MEM/REG and RD/WR are buffered transparently until the first falling edge of CLK after IOEN goes low. After this CLK edge, MEM/REG and
RD/WR become latched internally.
5.
The logic sense for RD/WR in the diagram assumes that POLARITY_SEL is connected to logic "1". If POLARITY_SEL is connected to logic "0",
RD/WR must be asserted low to read.
6.
The timing for IOEN, READYD and D15-D0 assumes a 50 pf load. For loading above 50 pf, the validity of IOEN, READYD, and D15-D0 is delayed
by an additional 0.14 ns/pf typ, 0.28 ns/pf max.
7.
The timing for A15-A0, MEM/REG and SELECT assumes that ADDR-LAT is connected to logic "1". Refer to Address Latch timing for additional
details.
8.
The address bus A15-A0 is internally buffered transparently until the first rising edge of CLK after IOEN goes low. After this CLK edge, A15-A0
become latched internally.
9.
Setup time given for use in worst case timing calculations. None of the Mark3’s input signals are required to be synchronized to the system clock.
When SELECT and STRBD do not meet the setup time of t1, but occur during the setup window of an internal flip-flop, an additional clock cycle
will be inserted between the falling clock edge that latches MEM/REG and RD/WR and the rising clock edge that latches the Address (A15-A0).
When this occurs, the delay from IOEN falling to READYD falling (t11) increases by one clock cycle and the address hold time (t10) must be
increased by one clock cycle.
相關(guān)PDF資料
PDF描述
BU-65142D1-240L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
BU-65142D1-260Q 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
BU-65142D1-340Y 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
BU-65142D1-370Y 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
BU-65142D1-370 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
BU-65-0 功能描述:測(cè)試電夾 ALLIGATOR CLIP BLK RoHS:否 制造商:Pomona Electronics 類(lèi)型:Minigrabber clip 顏色:Black
BU65-0 制造商:MUELLER ELECTRIC CO. 功能描述: 制造商:Mueller Electric Company 功能描述:
BU-651-0 功能描述:測(cè)試電夾 Black Shrouded Small RoHS:否 制造商:Pomona Electronics 類(lèi)型:Minigrabber clip 顏色:Black
BU-651-2 功能描述:測(cè)試電夾 Red Shrouded Small A RoHS:否 制造商:Pomona Electronics 類(lèi)型:Minigrabber clip 顏色:Black
BU65170G0-100 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Interface IC
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*