參數(shù)資料
型號： BT261KPJ
元件分類： TVS-瞬態(tài)抑制二極管
英文描述： Transient Voltage Suppressor Diodes
中文描述： 視頻信號發(fā)生器
文件頁數(shù)： 38/56頁
文件大?。?/td> 387K
代理商： BT261KPJ
Brooktree
32
L261_H
Bt261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
I
NTERNAL
R
EGISTERS
Noise Gate Start and Stop Registers
Noise Gate Start and Stop Registers
These two 16-bit registers specify the number of pixel clock cycles after the falling edge of CSYNC* at which to force
the noise gate to be closed (start value) or open (stop value). If [start value] = [stop value], the noise gate will remain
closed. The noise-gate start value should be activated no later than HCOUNT/2. The noise-gate stop value should be
within one half the minimum serration pulse width minus 500 ns to the end of the horizontal line. This gating is re-
quired because of the state counter that is used to determine the phase comparison output and the 500 ns delay that
is used for phase limiting. Because of this stop-value limitation, the digital noise gate can be used to track phase errors
no greater than one half the minimum serration pulse width. This translates into 2.3
μ
s and 0.75
μ
s (3.6 percent and
1.2 percent of the line rate) for RS170A and RS343, respectively. For example:
Note:
The Brooktree Applications Handbook and the RS343A and RS170A specifications contain minimum serration
pulse widths.
For wideband acquisition, the noise gate should be disabled by programming the start value greater and the stop
value less than the number of pixels per line.
Values from $0000 (1) to $0FFF (4096) may be specified. This register should be initialized early to minimize in-
determinate outputs during vertical retrace. This register must be properly programmed when the part is used in either
phase-lock loop mode or when an external oscillator is resynchronized.
D4–D7 of noise gate start high are ignored during MPU write cycles and return a logical zero during MPU read cy-
cles. The 16-bit noise gate start register is not updated until the write cycle to the noise gate start high register. Thus,
the writing sequence should be [noise gate start low] [noise gate start high].
D4–D7 of noise gate stop high are ignored during MPU write cycles and return a logical zero during MPU read cy-
cles. The 16-bit noise gate stop register is not updated until the write cycle to the noise gate stop high register. Thus,
the writing sequence should be [noise gate stop low] [noise gate stop high].
Video Source
1/2 Minimum Serration Pulse
261 Gate
Delay
Minimum Stop Value
From End of Line
Minimum Noise-Gate
Stop-Value Time
RS170A
2.3
μ
s
0,5
μ
s
1.8
μ
s
61,76
μ
s
RS343A
0,75
μ
s
0,5
μ
s
0,25
μ
s
63.31
μ
s
Noise Gate Start/Stop
High
Noise Gate Start/Stop Low
Data Bit
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Cascaded Value
H11
H19
H9
H8
H7
H6
H5
H4
H3
H2
H1
H0
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