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參數(shù)資料
| 型號(hào)： | BT261KPJ |
| 元件分類： | TVS-瞬態(tài)抑制二極管 |
| 英文描述： | Transient Voltage Suppressor Diodes |
| 中文描述： | 視頻信號(hào)發(fā)生器 |
| 文件頁數(shù)： | 15/56頁 |
| 文件大?。?/td> | 387K |
| 代理商： | BT261KPJ |
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Brooktree
9
C
IRCUIT
D
ESCRIPTION
External VCO Pixel Clock Generation
L261_H
Bt261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
External VCO Pixel Clock Generation
An external VCO or pixel clock may be used to drive the Bt261, as shown in
Figure 2. The pixel clock signal (from the VCO if one is used) is connected to any
one of the OSC input pins (the one used must be selected by command bits
CR00–CR02). When the clock pin is configured as an input, it must also be driven
by the pixel clock signal. The VCO must have positive control voltage (positive
voltage forces a higher frequency).
An on-chip phase comparator is available to compare the phase of HSYNC and
the falling edge of the noise-gated CSYNC*.
If the falling edge of the noise-gated CSYNC* occurs before the falling edge of
HSYNC, the phase comparator "dumps" a charge onto an external capacitor, in-
creasing the VCO frequency. If the falling edge of noise-gated CSYNC* occurs
after the falling edge of HSYNC, the phase comparator "sinks" a charge from the
external capacitor, decreasing the VCO frequency. Because of the internal delay el-
ements, the phase comparison occurs approximately 500 ns after the falling edge
of CSYNC*.
The output of the phase comparator is PCOUT and it is a TTL-compatible
three-statable output, which assumes a high-impedance state outside the
phase-comparison window. The width of the output pulse on PCOUT is equal to
the phase difference with a gain of 4
π
/VCC.
The "divide-by-N" for the PLL loop is the 12-bit HCOUNT register. Command
register bits CR07 and CR06 must be set to (1,0) for proper operation. This con-
figures the horizontal counter to be reset to zero upon reaching the HCOUNT val-
ue, which should be set to the number of pixels per line, minus 1.
Figure 2. External VCO Configuration.
VCO
PCOUT
Bt261
OSC (N)
CLOCK
Voltage Control
0 - 5 V
Second Order Loop Filter With
Zero Included for Loop Stability
C
2
C
3
R
3
R
4
R
5
HSYNC* lags CSYNC*
Increase Frequency (PCOUT = 5V)
No Change (PCOUT = High Impedance)
HSYNC* leads CSYNC*
Decrease Frequency (PCOUT = 0V)
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參數(shù)描述 |
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| BT-27 | 功能描述:TERM BLOCK HIGH CURRENT 27CIRC RoHS:是 類別:連接器，互連式 >> 接線座 - 隔板塊 系列:BT 標(biāo)準(zhǔn)包裝:10 系列:Beau™ 38780 端接塊類型:阻隔塊 電路數(shù):15 導(dǎo)線入口數(shù)目:30 間距:0.438"（11.12mm） 行數(shù):2 電流:15A 電壓:300V 線規(guī):14-22 AWG 頂部端子:螺釘 底部端子:焊片 阻擋層類型:雙壁（雙） 特點(diǎn):法蘭 顏色:黑 包裝:散裝 安裝類型:通孔 工作溫度:- 材料 - 絕緣體:聚對(duì)苯二甲酸丁二酯（PBT），玻璃纖維增強(qiáng)型 材料可燃性額定值:UL94 V-0 其它名稱:038780-111538780-1115387801115 |
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