參數(shù)資料
型號: BT261KPJ
元件分類: TVS-瞬態(tài)抑制二極管
英文描述: Transient Voltage Suppressor Diodes
中文描述: 視頻信號發(fā)生器
文件頁數(shù): 23/56頁
文件大?。?/td> 387K
代理商: BT261KPJ
Brooktree
17
C
IRCUIT
D
ESCRIPTION
Asynchronous (Unlocked) Pixel Clock Generation
L261_H
Bt261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
If a falling edge of the noise-gated CSYNC* occurs before the number of pixel
clock cycles specified by HCOUNT, the horizontal counter is reset to zero by the
falling edge of the noise-gated CSYNC*. CLOCK will be continuous and is re-
synchronized to each falling edge of the noise-gated CSYNC*. This mode is used
if the number of pixel clock cycles per scan line is known and is a fixed number.
CR07 and CR06 are (1,1): if a falling edge of the noise-gated CSYNC* does
not occur before the number of pixel clock cycles specified by HCOUNT, the hor-
izontal counter is reset to zero upon reaching HCOUNT, and begins incrementing
again, until the next falling edge of the noise-gated CSYNC* or HCOUNT value
is reached. CLOCK is continuous and is resynchronized to each falling edge of the
noise-gated CSYNC*.
If a falling edge of the noise-gated CSYNC* occurs before the number of pixel
clock cycles specified by HCOUNT, the horizontal counter is cleared at the falling
edge of the noise-gated CSYNC*, and begins incrementing again, until the next
falling edge of the noise-gated CSYNC* or HCOUNT value is reached. CLOCK
will be continuous and is resynchronized to the falling edge of the noise-gated
CSYNC*. This mode is used if the number of pixel clock cycles per scan line is not
known or an arbitrary value is to be used.
CR07 and CR06 are (1,0): Resets H counter at HCOUNT only.
Figure 7. Pixel Clock Output Timing When Generated From Higher Speed
Oscillator
OSC Count
Low
OSC Count
High
Noise-Gated
CSYNC
Clock
OSC
Clock Cycle Restarted
HCOUNT
Noise-Gated
CSYNC
Clock
HCOUNT
Detail
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