參數(shù)資料
型號: BT261KPJ
元件分類: TVS-瞬態(tài)抑制二極管
英文描述: Transient Voltage Suppressor Diodes
中文描述: 視頻信號發(fā)生器
文件頁數(shù): 37/56頁
文件大?。?/td> 387K
代理商: BT261KPJ
Brooktree
31
L261_H
I
NTERNAL
R
EGISTERS
FIELD Gate Start and Stop Registers
Bt261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
FIELD Gate Start and Stop Registers
These two 16-bit registers specify the number of pixel clock cycles after the falling edge of noise-gated CSYNC* at
which to start and stop the FIELD gate "window." With the noise gate properly programmed to ignore half-line ver-
tical interval pulses, the VSYNC* transition will occur half a line later during the vertical sync interval between fields
one and two (assuming a typical 2:1 interlaced video signal). By programming the FIELD start and stop values to
have an interval exceeding half a line (e.g. starting at 1/4 line time and stopping at 3/4 line time), the FIELD output
is low during field one if [start value] < [stop value] or high during field one if [start value] > [stop value], with tran-
sitions at every falling edge of VSYNC*. If [start value] = [stop value], FIELD will remain a constant logical one.
Values from $0000 (1) to $0FFF (4096) may be specified. Field edge coincides with VSYNC* falling edge.
D4–D7 of FIELD gate start high are ignored during MPU write cycles and return a logical zero during MPU read
cycles. The 16-bit FIELD gate start register is not updated until the write cycle to the FIELD gate start high register.
Thus, the writing sequence should be [field gate start low] [field gate start high].
D4–D7 of FIELD gate stop high are ignored during MPU write cycles and return a logical zero during MPU read
cycles. The 16-bit FIELD gate stop register is not updated until the write cycle to the FIELD gate stop high register.
Thus, the writing sequence should be [field gate stop low] [field gate stop high].
Values of one fourth HCOUNT and three fourths HCOUNT are recommended for start and stop values, resulting
in an active high FIELD output (field one = 1, field two = 0).
FIELD Gate Start/Stop
High
FIELD Gate Start/Stop Low
Data Bit
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Cascaded Value
H11
H19
H9
H8
H7
H6
H5
H4
H3
H2
H1
H0
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