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參數(shù)資料
| 型號： | BS616UV1010DCG10 |
| 廠商： | BRILLIANCE SEMICONDUCTOR, INC. |
| 英文描述： | Ultra Low Power CMOS SRAM 64K X 16 bit |
| 中文描述： | 超低功耗CMOS SRAM 64K的× 16位 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 218K |
| 代理商： | BS616UV1010DCG10 |
BS616UV1010
R0201-BS616UV1010
Revision
May.
2.6
2006
4
n
DATA RETENTION CHARACTERISTICS (T
A
= -40
O
C to +85
O
C)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.
(1)
MAX.
UNITS
V
DR
V
CC
for Data Retention
CE
≧
V
CC
-0.2V
V
IN
≧
V
CC
-0.2V or V
IN
≦
0.2V
1.5
--
--
V
I
CCDR
(3)
Data Retention Current
CE
≧
V
CC
-0.2V
V
IN
≧
V
CC
-0.2V or V
IN
≦
0.2V
--
0.01
0.5
uA
t
CDR
Chip Deselect to Data
Retention Time
0
--
--
ns
t
R
Operation Recovery Time
See Retention Waveform
t
RC
(2)
--
--
ns
1. V
CC
=1.5V, T
=25
O
C and not 100% tested.
2. t
RC
= Read Cycle Time.
3. I
CCDR(Max.)
is 0.2uA at T
A
=70
O
C.
n
LOW V
CC
DATA RETENTION WAVEFORM (CE Controlled)
n
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
1V/ns
Input and Output Timing
Reference Level
0.5Vcc
t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
WHZ
C
L
= 5pF+1TTL
Output Load
Others
C
L
= 30pF+1TTL
1. Including jig and scope capacitance.
n
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM
“
H
”
TO
“
L
”
WILL BE CHANGE
FROM
“
H
”
TO
“
L
”
MAY CHANGE
FROM
“
L
”
TO
“
H
”
WILL BE CHANGE
FROM
“
L
”
TO
“
H
”
DON
’
T CARE
ANY CHANGE
PERMITTED
CHANGE :
STATE UNKNOW
DOES NOT
APPLY
CENTER LINE IS
HIGH INPEDANCE
“
OFF
”
STATE
Data Retention Mode
V
DR
≧
1.5V
V
CC
t
CDR
V
CC
t
R
V
IH
V
IH
CE
≧
V
CC
- 0.2V
CE
V
CC
C
L
(1)
1 TTL
Output
ALL INPUT PULSES
→
←
Rise Time:
1V/ns
90%
V
CC
GND
Fall Time:
1V/ns
90%
→
←
10%
10%
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