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參數(shù)資料
| 型號： | BS616UV1010DCG10 |
| 廠商： | BRILLIANCE SEMICONDUCTOR, INC. |
| 英文描述： | Ultra Low Power CMOS SRAM 64K X 16 bit |
| 中文描述： | 超低功耗CMOS SRAM 64K的× 16位 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 218K |
| 代理商： | BS616UV1010DCG10 |
BS616UV1010
R0201-BS616UV1010
Revision
May.
2.6
2006
8
WRITE CYCLE 2
(1,6)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All
signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition
edge of the signal that terminates the write.
3. t
WR
is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = V
IL
).
7. D
OUT
is the same phase of write data of this write cycle.
8. D
OUT
is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals
of opposite phase to the outputs must not be applied to them.
10. Transition is measured
±
500mV from steady state with C
L
= 5pF.
The parameter is guaranteed but not 100% tested.
11.
CW
is measured from the later of CE going low to the end of write.
12. The change of Read/Write cycle must accompany with CE or address toggled.
t
WC
t
CW
(11)
t
WP
(2)
t
AW
t
WHZ
(4,10)
t
AS
t
WR2
(3)
t
DH
t
DW
D
IN
D
OUT
WE
LB, UB
CE
ADDRESS
(5)
t
OW
(7)
(8)
(8,9)
t
BW
(12)
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