參數(shù)資料
型號(hào): BS616UV1010DCG10
廠商: BRILLIANCE SEMICONDUCTOR, INC.
英文描述: Ultra Low Power CMOS SRAM 64K X 16 bit
中文描述: 超低功耗CMOS SRAM 64K的× 16位
文件頁(yè)數(shù): 2/11頁(yè)
文件大?。?/td> 218K
代理商: BS616UV1010DCG10
BS616UV1010
R0201-BS616UV1010
Revision
May.
2.6
2006
2
n
PIN DESCRIPTIONS
Name
Function
A0-A15 Address Input
These 16 address inputs select one of the 65,536 x 16-bit in the RAM
CE Chip Enable Input
CE is active LOW. Chip enable must be active when data read form or write to the
device. If chip enable is not active, the device is deselected and is in standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
Lower byte and upper byte data input/output control pins.
WE Write Enable Input
OE Output Enable Input
LB and UB Data Byte Control Input
DQ0-DQ15 Data Input/Output
Ports
V
CC
There 16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
V
SS
Ground
n
TRUTH TABLE
MODE
CE
WE
OE
LB
UB
IO0~IO7
IO8~IO15
V
CC
CURRENT
H
X
X
X
X
High Z
High Z
I
CCSB
, I
CCSB1
Chip De-selected
(Power Down)
X
X
X
H
H
High Z
High Z
I
CCSB
, I
CCSB1
L
H
H
L
X
High Z
High Z
I
CC
Output Disabled
L
H
H
X
L
High Z
High Z
I
CC
L
L
D
OUT
D
OUT
I
CC
H
L
High Z
D
OUT
I
CC
Read
L
H
L
L
H
D
OUT
High Z
I
CC
L
L
D
IN
D
IN
I
CC
H
L
X
D
IN
I
CC
Write
L
L
X
L
H
D
IN
X
I
CC
NOTES: H means V
IH
; L means V
IL
; X means don
t care (Must be V
IH
or V
IL
state)
相關(guān)PDF資料
PDF描述
BS616UV1010DCP10 Ultra Low Power CMOS SRAM 64K X 16 bit
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